REV. 5.1.0 ECR Bit-2: When low, this bit (ServiceIntr) enables a pulsed interrup" />
參數(shù)資料
型號: ST78C36CJ44TR-F
廠商: Exar Corporation
文件頁數(shù): 2/27頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B 44PLCC
標(biāo)準(zhǔn)包裝: 500
特點: *
FIFO's: 16 字節(jié)
規(guī)程: 打印機
電源電壓: 5V
帶并行端口:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
ST78C36/36A
10
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
REV. 5.1.0
ECR Bit-2:
When low, this bit (ServiceIntr) enables a pulsed interrupt and enables DMA requests (if bit-3 is set). If the
enabled interrupt occurs, this bit is automatically returned to a high. The interrupt conditions are:
ECR Bit-3 = DMA
DCR Bit-5 = DIRection
TABLE 3: DMA CONDITION
0
8 empty bytes in the FIFO
0
1
8 filled bytes in the FIFO
1
X
DMA Terminal Count (TC).
ECR BIT-3:
This bit disables DMA when set low. When set high, a low on ServiceIntr will enable DMA requests.
0 = DMA disabled, DRQx pin is three-stated.
1 = DMA enabled
ECR Bit-4:
When low, this bit (-ErrIntrEn) enables a pulsed interrupt if -ERROR (-Fault) is low. The interrupt is only
enabled in ECP mode.
ECR Bits 7-5:
This field can be set to any value if the current value is 000 or 001. If the current value is not 000 or 001, then
the field can only be written to 000 or 001. The modes are defined as:
TABLE 4: DESCRIPTION OF PARALLEL PORT MODES
000
SPP
Standard Centronics, output only. DCR bit-5 is forced to "0".
001
PS2
Bi-directional PS/2 parallel port. FIFO is disabled
010
PPF
FIFOed, output only. DCR Bit-5 is forced to “0”.
011
ECP
ECP FIFOed port with RLE de-compression. FIFO direction is controlled by DCR Bit-5.
100
EPP
EPP mode.
101
-
Reserved.
110
TST
FIFO test mode. FIFO is accessible via TFIFO register.
111
CFG
Configuration A/B register enable.
DMA
DIR
CONDITION
MODE
NAME
DESCRIPTION
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