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參數資料
| 型號： | ST92195C4B1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-56 |
| 文件頁數： | 106/250頁 |
| 文件大?。?/td> | 3010K |
| 代理商： | ST92195C4B1/XXX |
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ST92195 ST92T195 ST92E195 - TWO-CHANNEL I2C BUS INTERFACE (I2C)
I2C BUS INTERFACE (Cont’d)
Bit 6 = ARB_LOST
Arbitration LOST detection bit
This bit indicates if an arbitration lost occurred on
the bus.
0: No arbitration lost occurred
1: An arbitration lost occurred. The bit is set when
the interface operating as a master loses arbi-
tration to another master on the bus.
If a loss of arbitration occurs during the address
byte and if the interface has been addressed by
the winning master (ACT_SLV=1), then the
ARB_LOST flag is cleared by any “data load”
operation into I2CDR.
In all other cases it is up to the user to return
the interface into the status of an inactive slave
via either a CLEAR operation, a “Return To In-
active State” operation or a STOP request.
If a loss of arbitration occurs, an interrupt is
generated: when occurring during the address
byte, the interrupt is generated at the end of the
acknowledge bit; when occurring during a data
byte, the interrupt is generated immediately.
Note: the ERROR bit has higher priority than the
ARB_LOST bit (i.e. when ERROR=1, the value of
ARB_LOST has to be ignored).
Bit 5 = READ
Read/write status bit
This flag represents the state of the read/write bit
of the address byte. It is updated either for a mas-
ter or an active slave after the end of the address
byte. It is cleared, when the interface returns to the
inactive slave status (i.e. after the normal comple-
tion of a transaction, when exiting from any error
state, ...).
0: Write operation
1: Read operation
Bit 4 = FIRST
transmission status bit
This bit indicates if the byte transmitted on the bus
is an address byte or a data byte.
0: The byte is a data byte
1: The byte is the address part of an I2C bus trans-
action.
Note: the FIRST bit is automatically cleared at the
end of the interrupt, after the address, and when
the interface returns into inactive slave state.
Bit 3 = GEN_CALL
General CALL status bit
This bit indicates if a general call has been detect-
ed on the bus.
This bit is updated only if GENC_ACK=0 (see
I2CCTR register for more details)
0: No general call detected, or GENC_ACK=1.
1: The general call address 00h has been recog-
nized by the slave.
Note: This bit is cleared by hardware when the in-
terface returns to the inactive slave status.
Bit 2 = ACK_BIT
Acknowledge BIT
This bit reflects the logic level of the acknowledge
bit detected at the end of the last byte (either ad-
dress or data) transmitted on the I2C bus. It re-
mains valid until the interface exits from the inter-
rupt state.
0: Acknowledge detected
1: No acknowledge detected
Bit 1 = ACT_SLV
Active Slave status bit
This bit indicates the slave status of the interface.
0: The interface is not working in slave mode. It
may be inactive or in master mode (see the
ACTIVE bit for more details).
1: The address assigned to the interface has been
received on the bus and has been acknowl-
edged by the interface (SEND_ACK=0).
Note: This bit is cleared when the interface returns
into inactive slave state.
Bit 0 = ACTIVE
Interface Activity status bit
This bit indicates if the interface is active or not.
0: The I2C interface is inactive
1: The Interface is active. The bit is set throughout
the interval between a start condition and the
first stop condition that follows on the I2C bus.
Note: It is reset by the CLEAR bit.
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