- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98147 > ST92195C4B1/XXX (STMICROELECTRONICS) 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PDIP56 PDF資料下載
參數(shù)資料
| 型號(hào)： | ST92195C4B1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-56 |
| 文件頁(yè)數(shù)： | 85/250頁(yè) |
| 文件大?。?/td> | 3010K |
| 代理商： | ST92195C4B1/XXX |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)當(dāng)前第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)
175/249
ST92195 ST92T195 ST92E195 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.9.3 Functional Description
The SPI, when enabled, receives input data from
the internal data bus to the SPI Data Register
(SPIDR). A Serial Clock (SCK) is generated by
controlling through software two bits in the SPI
Control Register (SPICR). The data is parallel
loaded into the 8 bit shift register during a write cy-
cle. This is shifted out serially via the SDO pin,
MSB first, to the slave device, which responds by
sending its data to the master device via the SDI
pin. This implies full duplex transmission if 3 I/O
pins are used with both the data-out and data-in
synchronized with the same clock signal, SCK.
Thus the transmitted byte is replaced by the re-
ceived byte, eliminating the need for separate “Tx
empty” and “Rx full” status bits.
When the shift register is loaded, data is parallel
transferred to the read buffer and becomes availa-
ble to the CPU during a subsequent read cycle.
The SPI requires three I/O port pins:
SCK
Serial Clock signal
SDO
Serial Data Out
SDI
Serial Data In
An additional I/O port output bit may be used as a
slave chip select signal. Data and Clock pins IC
Bus protocol are open-drain to allow arbitration
and multiplexing.
Figure 93 below shows a typical SPI network.
Figure 94. A Typical SPI Network
n
7.9.3.1 Input Signal Description
Serial Data In (SDI)
Data is transferred serially from a slave to a mas-
ter on this line, most significant bit first. In an S-
BUS/I2C-bus configuration, the SDI line senses
the value forced on the data line (by SDO or by an-
other peripheral connected to the S-bus/I2C-bus).
7.9.3.2 Output Signal Description
Serial Data Out (SDO)
The SDO pin is configured as an output for the
master device. This is obtained by programming
the corresponding I/O pin as an output alternate
function. Data is transferred serially from a master
to a slave on SDO, most significant bit first. The
master device always allows data to be applied on
the SDO line one half cycle before the clock edge,
in order to latch the data for the slave device. The
SDO pin is forced to high impedance when the SPI
is disabled.
During an S-Bus or I2C-Bus protocol, when arbi-
tration is lost, SDO is set to one (thus not driving
the line, as SDO is configured as an open drain).
Master Serial Clock (SCK)
The master device uses SCK to latch the incoming
data on the SDI line. This pin is forced to a high im-
pedance state when SPI is disabled (SPEN,
SPICR.7 = “0”), in order to avoid clock contention
from different masters in a multi-master system.
The master device generates the SCK clock from
INTCLK. The SCK clock is used to synchronize
data transfer, both in to and out of the device,
through its SDI and SDO pins. The SCK clock
type, and its relationship with data is controlled by
the CPOL (Clock Polarity) and CPHA (Clock
Phase) bits in the Serial Peripheral Control Regis-
ter (SPICR). This input is provided with a digital fil-
ter which eliminates spikes lasting less than one
INTCLK period.
Two bits, SPR1 and SPR0, in the Serial Peripheral
Control Register (SPICR), select the clock rate.
Four frequencies can be selected, two in the high
frequency range (mostly used with the SPI proto-
col) and two in the medium frequency range
(mostly used with more complex protocols).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST9291N3 | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP56 |
| ST9291N6 | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP56 |
| ST92E141K4D1 | 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32 |
| ST92F120JV1T | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64 |
| ST92F120V6T | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST92195C4T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER |
| ST92195C5 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER |
| ST92195C5B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER |
| ST92195C5T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER |
| ST92195C6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。