
MDL110
3-337
SEC ASIC
FD4/FD4D2
D Flip-Flop with Reset, Set, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements
(Typical process, 25
°
C, 2.5V, Unit = ns)
Value (ns)
FD4
0.258
0.168
0.377
0.337
0.278
0.287
0.000
0.818
0.000
0.270
0.000
0.231
Input Load (SL)
Gate Count
FD4
FD4
FD4D2
FD4D2
D
0.6
CK
0.5
RN
1.5
SN
1.6
D
0.5
CK
0.5
RN
1.5
SN
1.5
6.67
7.00
Parameter
Symbol
FD4D2
0.255
0.189
0.372
0.364
0.316
0.327
0.000
0.802
0.000
0.281
0.000
0.221
Input Setup Time (D to CK)
Input Hold Time (D to CK)
Pulse Width Low (CK)
Pulse Width High (CK)
Pulse Width Low (RN)
Pulse Width Low (SN)
Recovery Time (RN to CK)
Removal Time (RN to CK)
Recovery Time (SN to CK)
Removal Time (SN to CK)
Removal Time (SN to RN)
Recovery Time (SN to RN)
t
SU
t
HD
t
PWL
t
PWH
t
PWL
t
PWL
t
RC
t
RM
t
RC
t
RM
t
RM
t
RC
D
CK
Q
QN
RN
SN
D
CK
CL
CLB
Q
CL
CLB
CL
CLB
CL
CL
CLB
QN
CLB
SN
SN
RN
RN
RN
RN
SN
SN
Truth Table
D
CK
RN
SN
Q
(n+1)
0
1
1
0
0
Q (n)
QN
(n+1)
1
0
0
1
0
QN (n)
0
1
x
x
x
x
1
1
1
0
0
1
1
1
0
1
0
1
x
x
x