
MDL110
3-355
SEC ASIC
FD5S/FD5SD2
D Flip-Flop with Negative Edge Trigger, Scan, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements
(Typical process, 25
°
C, 2.5V, Unit = ns)
Value (ns)
FD5S
0.511
0.323
0.316
0.316
0.423
0.253
0.377
0.338
Input Load (SL)
Gate Count
FD5S
FD5S
FD5SD2
CKN
0.5
FD5SD2
D
0.4
CKN
0.6
TI
0.5
TE
1.2
D
0.4
TI
0.5
TE
1.1
6.67
7.00
Parameter
Symbol
FD5SD2
0.492
0.320
0.326
0.326
0.413
0.249
0.359
0.343
Input Setup Time (D to CKN)
Input Hold Time (D to CKN)
Pulse Width Low (CKN)
Pulse Width High (CKN)
Input Setup Time (TI to CKN)
Input Hold Time (TI to CKN)
Input Setup Time (TE to CKN)
Input Hold Time (TE to CKN)
t
SU
t
HD
t
PWL
t
PWH
t
SU
t
HD
t
SU
t
HD
Q
QN
D
TI
TE
CKN
CLN
CLBN
CLBN
CLN
CLN
CLBN
CLN
CLBN
TE
TEB
TE
Q
QN
D
TE
TI
TEB
CLN
CLBN
CKN
Truth Table
D
TI
TE
CKN
Q
(n+1)
0
1
0
1
Q (n)
QN
(n+1)
1
0
1
0
QN (n)
0
1
x
x
x
x
x
0
1
x
0
0
1
1
x