參數(shù)資料
型號(hào)： STK17CA8-W45I
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： REAL TIME CLOCK, PDIP40
封裝： 0.600 INCH, DIP-40
文件頁(yè)數(shù)： 3/22頁(yè)
文件大?。?/td> 579K
代理商： STK17CA8-W45I
STK17CA8
June 2003
11
Document Control # ML0023 rev 0.2
RECALL
cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a
busy condition while the STORE (initiated by any
means) is in progress.
SRAM READ
and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK17CA8 will
continue SRAM operations for t
DELAY. During tDELAY,
multiple SRAM READ operations may take place. If a
WRITE
is in progress when HSB is pulled low it will
be allowed a time, t
DELAY, to complete. However, any
SRAM WRITE
cycles requested after HSB goes low
will be inhibited until HSB returns high.
The HSB pin can be used to synchronize one
STK17CA8 with one or more STK14CA8 nvSRAMs
to expand the memory space. To operate in this
mode the HSB pins from each device should be
connected together. An external pull-up resistor to +
3.0V is required since HSB acts as an open drain
pull down. The V
CAP pins from the other parts can be
tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
devices detects a power loss and asserts HSB, the
common HSB pin will cause all parts to request a
STORE
cycle (a STORE will take place in those
devices that have been written since the last nonvol-
atile cycle).
During any STORE operation, regardless of how it
was initiated, the STK17CA8 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK17CA8 will remain disabled until the HSB
pin returns high.
If HSB is not used, it should be left unconnected.
POWER-UP RECALL
During power up, or after any low-power condition
(V
CCX < VSWITCH), an internal RECALL request will be
latched. When V
CAP once again exceeds the sense
voltage of V
SWITCH, a RECALL cycle will automatically
be initiated and will take t
RESTORE to complete.
If the STK17CA8 is in a WRITE state at the end of
power-up RECALL, the WRITE will be inhibited and E
or W must be brought high and then low for a write
to initiate.
SOFTWARE NONVOLATILE STORE
The STK17CA8 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations. During the STORE
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvol-
atile elements. The program operation copies the
SRAM
data into nonvolatile memory. Once a STORE
cycle is initiated, further input and output are dis-
abled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence, or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ
sequence must be performed:
1. Read address
4E38 (hex)
Valid READ
2. Read address
B1C7 (hex)
Valid READ
3. Read address
83E0 (hex)
Valid READ
4. Read address
7C1F (hex)
Valid READ
5. Read address
703F (hex)
Valid READ
6. Read address
8FC0 (hex)
Initiate STORE cycle
The software sequence may be clocked with E con-
trolled READs or G controlled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the t
STORE cycle time has
been fulfilled, the SRAM will again be activated for
READ
and WRITE operation.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of E controlled READ opera-
tions must be performed:
1. Read address
4E38 (hex)
Valid READ
2. Read address
B1C7 (hex)
Valid READ
3. Read address
83E0 (hex)
Valid READ
4. Read address
7C1F (hex)
Valid READ
5. Read address
703F (hex)
Valid READ
6. Read address
4C63 (hex)
Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the
SRAM
data is cleared, and second, the nonvolatile
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