參數(shù)資料
型號: STK17CA8-W45I
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: REAL TIME CLOCK, PDIP40
封裝: 0.600 INCH, DIP-40
文件頁數(shù): 4/22頁
文件大小: 579K
代理商: STK17CA8-W45I
STK17CA8
June 2003
12
Document Control # ML0023 rev 0.2
information is transferred into the SRAM cells. After
the t
RECALL cycle time the SRAM will once again be
ready for READ and WRITE operations. The RECALL
operation in no way alters the data in the nonvolatile
elements.
PREVENTING STORES
The AutoStore function can be disabled by initiat-
ing an AutoStore Inhibit sequence. A sequence of
read operations is performed in a manner similar to
the software STORE initiation. To initiate the
AutoStore Inihibit sequence, the following sequence
of E controlled read operations must be performed:
1. Read address
4E38 (hex)
Valid READ
2. Read address
B1C7 (hex)
Valid READ
3. Read address
83E0 (hex)
Valid READ
4. Read address
7C1F (hex)
Valid READ
5. Read address
703F (hex)
Valid READ
6. Read address
8B45 (hex)
AutoStore Inhibit
The AutoStore Inhibit can be disabled by initiating
an AutoStore Inhibit Off sequence. A sequence of
read operations is performed in a manner similar to
the software RECALL initiation. To initiate the
AutoStore Inhibit Off sequence, the following
sequence of E controlled read operations must be
performed:
1. Read address
4E38 (hex)
Valid READ
2. Read address
B1C7 (hex)
Valid READ
3. Read address
83E0 (hex)
Valid READ
4. Read address
7C1F (hex)
Valid READ
5. Read address
703F (hex)
Valid READ
6. Read address
4B46 (hex)
AutoStore Inhibit Off
The last AutoStore Inhibit state is stored in nonvola-
tile memory and is retained through power cycling.
NOISE CONSIDERATIONS
The STK17CA8 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1
F connected between V
CAP and
V
SS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
HARDWARE WRITE PROTECT
The STK17CA8 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs dur-
ing low-voltage conditions. When V
CCX < VSWITCH, all
externally initiated STORE operations and SRAM
WRITE
s will be inhibited.
LOW AVERAGE ACTIVE POWER
The STK17CA8 draws significantly less current
when it is cycled at times longer than 50ns. Figure 3
shows the relationship between I
CC and READ cycle
time. Worst-case current consumption is shown for
commercial temperature range, V
CC = 3.6V, and
100% duty cycle on chip enable. Figure 4 shows the
same relationship for WRITE cycles. If the chip
enable duty cycle is less than 100%, only standby
current is drawn when the chip is disabled. The
overall average current drawn by the STK17CA8
depends on the following items: 1) the duty cycle of
chip enable; 2) the overall cycle rate for accesses;
3) the ratio of READs to WRITEs; 4) the operating
temperature; 5) the Vcc level; and 6) I/O loading.
Figure 3: Icc (max) Reads
Figure 4: Icc (max) Writes
0
10
20
30
40
50
100
150
200
Cycle Time (ns)
A
vera
ge
Acti
ve
Cu
rren
t(m
A)
0
10
20
30
40
50
100
150
200
Cycle Time (ns)
A
vera
g
e
A
ctive
Cu
rren
t(m
A
)
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