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參數(shù)資料
| 型號(hào)： | STPC0375BTI3 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | PC Compatible Embeded Microprocessor |
| 中文描述： | PC兼容嵌入式微處理器 |
| 文件頁(yè)數(shù)： | 29/51頁(yè) |
| 文件大小： | 726K |
| 代理商： | STPC0375BTI3 |
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STRAP OPTION
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Issue 1.2
Bit 1 This bit reflects the
value sampled on
MD[17] pin
and controls the PCI clock output as
follows:
0: PCI clock output = HCLK / 2
1: PCI clock output = HCLK / 3
Bit 0; Reserved
This register defaults to the values sampled on
MD[23] & MD[20:16] pins after reset.
3.1.4 HCLK PLL STRAP REGISTER 0 INDEX
5FH (HCLK_STRAP0)
Bits 5-0 of this register reflect the status of pins
MD[26:21] respectively. They are use by the chip
as follows:
Bits 5-3; These pins reflect the
value sampled on
MD[26:24] pins
respectively and control the Host
clock frequency synthesizer.
Bit 2-0; Reserved
This register defaults to the values sampled on
above pins after reset.
Strap Options [39:27] are reserved.
3.1.5 486 CLOCK PROGRAMMING (486_CLK)
The bit MD[40] is used to set the clock multiplica-
tion factor of the 486 core. With the MD[40] pin
pulled low the 486 will run in DX (x1) mode, while
with the MD[40] pin pulled high the 486 will run in
DX2 (x2) mode. The default value of the resistor
on this strap input should be a resister to ground
(DX mode).
Strap options MD[43:41] are reserved.
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