th May 2012 www.semtech.com 21 SX1501/SX1502/SX1503 4/8/16 Channel L" />
參數(shù)資料
型號： SX1503I091TRT
廠商： Semtech
文件頁數(shù)： 14/32頁
文件大?。?/td> 0K
描述： IC GPIO EXPANDER I2C 16CH 28-QFN
產(chǎn)品培訓(xùn)模塊： Low Voltage GPIO Expander Family
標(biāo)準(zhǔn)包裝： 1
接口： I²C
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 1.2 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-UFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 28-QFN（4x4）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1359 (CN2011-ZH PDF)
其它名稱： SX1503I091DKR
WIRELESS & SENSING
Rev 11 – 16
th May 2012
www.semtech.com
21
SX1501/SX1502/SX1503
4/8/16 Channel Low Voltage GPIO
Addr
Name
Default
Bits
Description
RegEventStatus
3:0
Event status of all IOs.
0 : No event has occured on this IO
1 : An event has occured on this IO (an edge as configured in relevant RegSense
register occured).
Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant.
If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically
7:2
Reserved. Must be set to 0 (default value)
0x10
RegPLDMode
0x00
1:0
PLDMode
00 : PLD disabled – Normal GPIO mode for I/O[3:0]
01 : PLD 2-to-1 mode – I/O[2] is a decode of I/O[1:0] as defined in RegPLDTable0
10 : PLD 3-to-1 mode – I/O[3] is a decode of I/O[2:0] as defined in RegPLDTable2
11 : Not used
7:4
Reserved. Must be set to 0 (default value)
3
Value to be output on I/O[2] when I/O[1:0] = 11
2
Value to be output on I/O[2] when I/O[1:0] = 10
1
Value to be output on I/O[2] when I/O[1:0] = 01
0x11
RegPLDTable0
0x00
0
Value to be output on I/O[2] when I/O[1:0] = 00
Applies only when PLDMode is
set to PLD 2-to-1 mode
0x12
RegPLDTable1
0xXX
7:0
Unused
7
Value to be output on I/O[3] when I/O[2:0] = 111
6
Value to be output on I/O[3] when I/O[2:0] = 110
5
Value to be output on I/O[3] when I/O[2:0] = 101
4
Value to be output on I/O[3] when I/O[2:0] = 100
3
Value to be output on I/O[3] when I/O[2:0] = 011
2
Value to be output on I/O[3] when I/O[2:0] = 010
1
Value to be output on I/O[3] when I/O[2:0] = 001
0x13
RegPLDTable2
0x00
0
Value to be output on I/O[3] when I/O[2:0] = 000
Applies only when PLDMode is
set to PLD 3-to-1 mode
0x14
RegPLDTable3
0xXX
7:0
Unused
0x15
RegPLDTable4
0xXX
7:0
Unused
7.2
Reserved. Must be set to 0 (default value)
1
Boost Mode (Cf. §2.2.1)
0: OFF
1: ON
0xAB
RegAdvanced
0x00
0
Reserved. Must be set to 0 (default value)
Table 13 – SX1501 Configuration Registers Description
5.2
SX1502 8-channel GPIO
Address
Name
Description
Default
0x00
RegData
Data register
1111 1111
*
0x01
RegDir
Direction register
1111 1111
0x02
RegPullUp
Pull-up register
0000 0000
0x03
RegPullDown
Pull-down register
0000 0000
0x04
Reserved
Unused
XXXX XXXX
0x05
RegInterruptMask
Interrupt mask register
1111 1111
0x06
RegSenseHigh
Sense register for I/O[7:4]
0000 0000
0x07
RegSenseLow
Sense register for I/O[3:0]
0000 0000
0x08
RegInterruptSource
Interrupt source register
0000 0000
0x09
RegEventStatus
Event status register
0000 0000
0x10
RegPLDMode
PLD mode register
0000 0000
0x11
RegPLDTable0
PLD truth table 0
0000 0000
0x12
RegPLDTable1
PLD truth table 1
0000 0000
0x13
RegPLDTable2
PLD truth table 2
0000 0000
0x14
RegPLDTable3
PLD truth table 3
0000 0000
0x15
RegPLDTable4
PLD truth table 4
0000 0000
0xAB
RegAdvanced
Advanced settings register
0000 0000
*Bits set as output take “1” as default value.
Table 14 – SX1502 Configuration Registers Overview
Addr
Name
Default
Bits
Description
0x00
RegData
0xFF
7:0
Write: Data to be output to the output-configured IOs
Read: Data seen at the IOs, independent of the direction configured.
0x01
RegDir
0xFF
7:0
Configures direction for each IO.
0 : IO is configured as an output
1 : IO is configured as an input
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