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參數(shù)資料
| 型號(hào)： | SX1503I091TRT |
| 廠商： | Semtech |
| 文件頁數(shù)： | 7/32頁 |
| 文件大小： | 0K |
| 描述： | IC GPIO EXPANDER I2C 16CH 28-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Low Voltage GPIO Expander Family |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接口： | I²C |
| 輸入/輸出數(shù)： | 16 |
| 中斷輸出： | 是 |
| 頻率 - 時(shí)鐘： | 400kHz |
| 電源電壓： | 1.2 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-UFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1359 (CN2011-ZH PDF) |
| 其它名稱： | SX1503I091DKR |
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WIRELESS & SENSING
Rev 11 – 16
th May 2012
www.semtech.com
15
SX1501/SX1502/SX1503
4/8/16 Channel Low Voltage GPIO
4.
During a brown-out event, if VDDM drops above VDROPH a reset will not occur.
5.
During a brown-out event, if VDDM drops between VDROPH and VDROPL a reset may occur.
6.
During a brown-out event, if VDDM drops below VDROPL a reset will occur next time VPOR is crossed.
Please note that a brown-out event is defined as a transient event on VDDM. If VDDM is attached to a battery,
then the gradual decay of the battery voltage will not be interpreted as a brown-out event.
Please also note that a sharp rise in VDDM (> 1V/us) may induce a circuit reset.
4.5
2-Wire Interface (I
2C)
The SX1501, SX1502 and SX1503 2-wire interface (I
2C compliant) operates only in slave mode. In this
configuration, the device has one or two device addresses defined by ADDR pin.
Device
ADDR Pin
I
2C Address
Description
0
0x20 (0100000)
First address of the 2-wire interface
SX1501 &
SX1502
1
0x21 (0100001)
Second address of the 2-wire interface
SX1503
0x20 (0100000)
Fixed address of the 2-wire interface
Table 7 - 2-Wire Interface Address
2 lines are used to exchange data between an external master host and the slave device:
SCL : Serial CLock
SDA : Serial DAta
The SX1501, SX1502 and SX1503 are read-write slave-mode I
2C devices and comply with the Philips I2C
standard Version 2.1 dated January, 2000. The SX1501, SX1502 and SX1503 have respectively 12, 16, and 31
user-accessible internal 8-bit registers. The I
2C interface has been designed for program flexibility, in that once
the slave address has been sent to the SX1501, SX1502 or SX1503 enabling it to be a slave
transmitter/receiver, any register can be written or read independently of each other. While there is no auto
increment/decrement capability in the SX1501 and SX1502 I
2C logic, a tight software loop can be designed to
access the next register independent of which register you begin accessing. SX1503 implements auto increment
capability. The start and stop commands frame the data-packet and the repeat start condition is allowed if
necessary.
Seven bit addressing is used and ten bit addressing is not allowed. Any general call address will be ignored by
the SX1501, SX1502 and SX1503. The SX1501, SX1502 and SX1503 are not CBUS compatible and can
operate in standard mode (100kbit/s) or fast mode (400kbit/s).
4.5.1
WRITE
The simplest format for an I
2C write is given below. After the start condition [S], the slave address is sent,
followed by an eighth bit indicating a write. The I
2C then acknowledges that it is being addressed, and the master
responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master
sends the appropriate 8 bit data byte. Once again the slave acknowledges and the master terminates the
transfer with the stop condition [P].
Master operations
SX1501, SX1502 or SX1503 operations (Slave)
S: Start Condition
Slave Address: 7 bit
W: Write = ‘0’
Register Address: 8 bit
A: Acknowledge (sent by slave)
Data: 8 bit
P: Stop condition
Figure 8 - 2-Wire Serial Interface, Write Register Operation
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