th May 2012 www.semtech.com 8 SX1501/SX1502/SX1503 4/8/16 Channel Lo" />
參數(shù)資料
型號(hào): SX1503I091TRT
廠商: Semtech
文件頁(yè)數(shù): 31/32頁(yè)
文件大?。?/td> 0K
描述: IC GPIO EXPANDER I2C 16CH 28-QFN
產(chǎn)品培訓(xùn)模塊: Low Voltage GPIO Expander Family
標(biāo)準(zhǔn)包裝: 1
接口: I²C
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 1.2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-UFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 28-QFN(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1359 (CN2011-ZH PDF)
其它名稱(chēng): SX1503I091DKR
WIRELESS & SENSING
Rev 11 – 16
th May 2012
www.semtech.com
8
SX1501/SX1502/SX1503
4/8/16 Channel Low Voltage GPIO
Symbol
Description
Conditions
Min
Typ
Max
Unit
tIR
Interrupt reset timing
From RegInterruptSource
clearing
-
2
s
NRESET (Input/Output)
VOL
Low level output voltage
-
0.3
V
VDDM >= 2V
-
12
IOLM
Low level output sink current
VDDM < 2V
-
6
mA
VIHMR
High level input voltage
-
0.7*
VDDM
-
5.5
V
VILM
Low level input voltage
-
-0.4
-
0.3*
VDDM
V
VHYSM
Hysteresis of Schmitt trigger
-
0.1*
VDDM
-
V
ILEAK
Input leakage current
-
-1.5
-
1.5
A
CI
Input capacitance
-
10
pF
VPOR
Power-On-Reset voltage
Cf. Figure 7
0.7
-
0.9
V
VDROPH High brown-out voltage
Cf. Figure 7
-
VDDM-1
-
V
VDROPL Low brown-out voltage
Cf. Figure 7
-
0.2
-
V
tRESET
Reset time
Cf. Figure 7
-
7
ms
tPULSE
Reset pulse from host uC
Cf. Figure 7
300
-
ns
ADDR (Input)
VIHMA
High level input voltage
-
0.7*
VDDM
-
VDDM
+0.3
V
VILM
Low level input voltage
-
-0.4
-
0.3*
VDDM
V
VHYSM
Hysteresis of Schmitt trigger
-
0.1*
VDDM
-
V
ILEAK
Input leakage current
-
-1.5
-
1.5
A
CI
Input capacitance
-
10
pF
SCL (Input) and SDA (Input/Output)
(3)
Interface complies with slave F/S mode I
2C interface as described by Philips I2C specification version 2.1
dated January, 2000. Please refer to that document for more detailed I
2C specifications.
VOL
Low level output voltage
-
0.3
V
VDDM >= 2V
-
12
IOLM
Low level output sink current
VDDM < 2V
-
6
mA
VIHMR
High level input voltage
-
0.7*
VDDM
-
5.5
V
VILM
Low level input voltage
-
-0.4
-
0.3*
VDDM
V
fSCL
SCL clock frequency
-
0
-
400
kHz
tHD;STA
Hold time (repeated) START
condition
-
0.6
-
s
tLOW
LOW period of the SCL clock
-
1.3
-
s
VDDM >= 1.3V
0.6
-
tHIGH
HIGH period of the SCL clock
VDDM < 1.3V
1
-
s
tSU;STA
Set-up time for a repeated
START condition
-
0.6
-
s
tHD;DAT
Data hold time
-
0
(4)
-
0.9
(5)
s
tSU;DAT
Data set-up time
-
100
(6)
-
tr
Rise time of both SDA and
SCL signals
-
20+0.1Cb
(7)
-
300
ns
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