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參數(shù)資料
| 型號： | SY100E016JY TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 0K |
| 描述： | IC UPCOUNTER 8BIT SYNC 28-PLCC |
| 標準包裝： | 750 |
| 系列： | 100E |
| 邏輯類型： | 二進制計數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 8 |
| 復位： | 異步 |
| 計時： | 同步 |
| 計數(shù)速率： | 900MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.2 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY100E016JYTR SY100E016JYTR-ND |
6
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
APPLICATIONS INFORMATION
Cascading Multiple E016 Devices
For applications which call for larger than 8-bit counters,
multiple E016s can be tied together to achieve very wide bit
width counters. The active low terminal count (TC) output and
count enable input (CE) greatly facilitate the cascading of
E016 devices. Two E016s can be cascaded without the need
for external gating; however, for counters wider than 16 bits,
external OR gates are necessary for cascade implementations.
Figure 1, below, pictorially illustrates the cascading of 4
E016s to build a 32-bit high frequency counter. Note the E101
gates used to OR the terminal count outputs of the lower order
E016s to control the counting operation of the higher order
bits. When the terminal count of the preceding device (or
devices) goes low (the counter reaches an all 1s state), the
more significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transition. In
addition, the preceding devices will also count one bit, thus
sending their terminal count outputs back to a high state,
disabling the count operation of the more significant counters
and placing them back into hold modes. Therefore, for an
E016 in the chain to count all of the lower order terminal count
outputs, it must be in the low state. The bit width of the counter
can be increased or decreased by simply adding or subtracting
E016 devices from Figure 1 and maintaining the logic pattern
illustrated in the same figure.
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC output
and the necessary set-up time of the CE input and the
propagation delay through the OR gate controlling it (for 16-
bit counters the limitation is only the TC propagation delay and
the CE set-up time). Figure 1 shows E101 gates used to
control the count enable inputs; however, if the frequency of
operation is lower, a slower ECL OR gate can be used. Using
the worst case guarantees for these parameters from the
ECLinPS data book, the maximum count frequency for a
greater than 16-bit counter is 475MHz and that for a 16-bit
counter is 625MHz. Note that this assumes the trace delay
between the TC outputs and the CE inputs are negligible. If
this is not the case, estimates of these delays need to be
added to the calculations.
Figure 1. 32-Bit Cascaded E016 Counter
Q0–Q7
P0–P7
CE
PE
TC
CLK
E016
LSB
TC
CLK
E016
TC
CLK
E016
TC
CLK
E016
MSB
LOAD
"LO"
CLOCK
E101
Q0–Q7
P0–P7
CE
PE
CE
PE
CE
PE
E101
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