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參數(shù)資料
| 型號(hào)： | SY69753ALHG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA REC 125MBPS 32TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM OC-3 |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 155Mbps |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-EPAD-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY69753ALHGTR SY69753ALHGTR-ND |
Micrel, Inc.
SY69753AL
August 2007
6
M9999-082107-E
hbwhelp@micrel.com or (408) 955-1690
Functional Block
Functional Description
Clock Recovery
Clock Recovery, as shown in the block diagram,
generates a clock that is at the same frequency as the
incoming data bit rate at the Serial Data input. The
clock is phase aligned by a PLL so that it samples the
data in the center of the data eye pattern.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency detector. Output
pulses from the detector indicate the required
direction of phase correction. These pulses are
smoothed by an integral loop filter. The output of the
loop filter controls the frequency of the Voltage
Controlled Oscillator (VCO), which generates the
recovered clock.
Frequency
stability,
without
incoming
data,
is
guaranteed by an alternate reference input (REFCLK)
that the PLL locks onto when data is lost. If the
Frequency of the incoming signal varies by greater
than approximately 1000ppm with respect to the
synthesizer frequency, the PLL will be declared out of
lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET data
signal. This transfer function yields a 30s data
stream of continuous 1's or 0's for random incoming
NRZ data.
Lock Detect
The SY69753AL contains a link fault indication circuit,
which monitors the integrity of the serial data inputs. If
the received serial data fails the frequency test, then
the PLL will be forced to lock to the local reference
clock. This will maintain the correct frequency of the
recovered clock output under loss of signal or loss of
lock conditions. If the recovered clock frequency
deviates from the local reference clock frequency by
more than approximately 1000ppm, the PLL will be
declared out of lock. The lock detect circuit will poll the
input data stream in an attempt to reacquire lock to
data. If the recovered clock frequency is determined to
be within approximately 1000ppm, the PLL will be
declared in lock and the lock detect output will go
active.
During the interval when the CDR is not locked onto
the RDIN input, the LFIN output will not be a static
LOW, but will be changing.
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY69753L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 125Mbps, 155Mbps Clock and Data Recovery |
| SY69753L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 125Mbps, 155Mbps Clock and Data Recovery |
| SY69753L_07 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 125Mbps, 155Mbps Clock and Data Recovery |
| SY69753LHC | 功能描述:IC CLOCK/DATA RECVRY 3.3V 32TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| SY69753LHG | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 3.3V 155 Mbps CDR (I Temp, Green/32 pin TQFP) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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