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參數(shù)資料
| 型號(hào)： | SY69952A |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER |
| 中文描述： | OC-3/STS-3鐘回收收發(fā)器 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 97K |
| 代理商： | SY69952A |
SY69952A
2
Micrel
input data equalization in copper based systems, reducing
the system impact of data dependent jitter. All PECL outputs
can be powered down by connecting both outputs to VCC
or leaving them both unconnected.
RSER
±
– Differential PECL Output
Recovered Serial Data. These Positive ECL 100K outputs
(+5V referenced) represent the recovered data from the
input data stream (RIN
±
). This recovered data is aligned
with the recovered clock (RCLK
±
) with a sampling window
compatible with most data processing devices.
RCLK
±
– Differential PECL Output
Recovered Clock. These Positive ECL 100K outputs (+5V
referenced) represent the recovered clock from the input
data stream (RIN
±
). This recovered clock is used to sample
the recovered data (RSER
±
) and has timing compatible
with most data processing devices.
/LFI – TTL Output
Link Fault Indicator. This output indicates the status of
the input data stream (RIN
±
). It is controlled by three
functions; the Carrier Detect (CD) input, the internal
Transition Detector, and the Out of Lock (OOL) detector.
The Transition Detector determines if RIN
±
contains enough
transitions to be accurately recovered by the Receive PLL.
The Out of Lock detector determines if RIN
±
is within the
frequency range of the Receive PLL. When CD is HIGH
and RIN
±
has sufficient transitions and is within the
frequency range of the Receive PLL, the /LFI output will be
high. If CD is at an ECL LOW or RIN
±
does not contain
sufficient transitions or RIN
±
is outside the frequency range
of the Receive PLL then the /LFI output will be LOW. If CD
is at a TTL LOW then the /LFI output will only transition
LOW when the frequency of RIN
±
is outside the range of
the Receive PLL.
TOUT
±
– Differential PECL Output
Transmit Output. These Positive ECL 100K outputs (+5V
referenced) represent the buffered version of the Transmit
data stream (TSER
±
). This Transmit path is used to take
weak input signals and rebuffer them to drive low impedance
copper media.
TCLK
±
– Differential PECL Output
Transmit Clock. These Positive ECL 100K outputs (+5V
referenced) provide the bit rate frequency source for external
Transmit data processing devices. This output is synthesized
by the Transmit PLL and is derived by multiplying the
REFCLK frequency by eight.
INPUTS
RIN
±
– Differential PECL Input
Receive Input. These built-in line receiver inputs are
connected to the differential Receive serial input data stream.
An internal Receive PLL recovers the embedded clock
(RCLK
±
) and data (RSER
±
) information. The incoming data
rate can be within one of two frequency ranges, mentioned
before depending on the state of the MODE pin.
CD – PECL/TTL Input
Carrier Detect. This input controls the recovery function
of the Receive PLL and can be driven by the carrier detect
output from optical modules or from external transition
detection circuitry. When this input is at an ECL HIGH, the
input data stream (RIN
±
) is recovered normally by the
Receive PLL. When this input is at an ECL LOW, the
Receive PLL no longer aligns to RIN
±
, but instead aligns
with the REFCLK
×
8 frequency. Also, the Link Fault Indicator
(/LFI) will transition LOW, and the recovered data outputs
(RSER
±
) will remain LOW regardless of the signal level on
the Receive data stream inputs (RIN
±
). When the CD input
is at a TTL LOW (
≤
0.8V), the internal transition detection
circuitry is disabled. When in Loop-back testing mode,
regardless of the signal level on the CD input, the Receive
PLL is internally turned-on to allow data stream transmission
to the recovered serial data outputs (RSER
±
) from the
Transmit serial data inputs (TSER
±
).
TSER
±
– Differential PECL Input
Transmit Serial Data. These built-in line receiver inputs
are connected to the differential Transmit serial input data
stream. These inputs can receive very low amplitude signals
and are compatible with PECL signal levels.
REFCLK
±
– Differential PECL/TTL Input
Reference Clock. This input is the clock frequency
reference for the clock and data recovery Receive PLL.
REFCLK is multiplied internally by eight and sets the
approximate center frequency for the internal Receive PLL
to track the incoming bit stream. This input is also multiplied
by eight by the frequency multiplier Transmit PLL to produce
the bit rate Transmit Clock (TCLK
±
). REFCLK can be
connected to either a differential PECL or single-ended TTL
frequency source. When either REFCLK+ or REFCLK- is at
a TTL LOW, the opposite REFCLK signal becomes a TTL
level input.
OUTPUTS
ROUT
±
– Differential PECL Output
Receive Output. These Positive ECL 100K outputs (+5V
referenced) represent the buffered version of the input data
stream (RIN
±
). This output pair can be used for Receiver
PIN DESCRIPTIONS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY69952AZC | High Efficient Rectifier Diodes |
| SY69952 | Raised Panel Label; External Height:0.49"; External Width:1.06"; Label Material:Polyester; Color:Yellow; Features:Foam-Backed Raised Design; Permanent Acrylic Adhesive; Thermal Transfer Print Quality RoHS Compliant: Yes |
| SY69952ZC | OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER |
| SY87700L | 3.3V 32-175Mbps AnyRate⑩ CLOCK AND DATA RECOVERY |
| SY87700VZC | 5V/3.3V 32-175Mbps AnyRate⑩ CLOCK AND DATA RECOVERY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY69952AZC | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ATM/SONET TRANSCEIVER|SOP|28PIN|PLASTIC |
| SY69952ZC | 功能描述:IC TXRX CLOCK RECOVERY 28-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| SY69952ZC TR | 功能描述:IC TXRX CLOCK RECOVERY 28-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| SY69952ZH | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 OC-3/STS-3 Clock Recovering Transceiver (Green) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SY69952ZH TR | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 OC-3/STS-3 Clock Recovering Transceiver (Green) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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