- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385893 > SY87701VZHTR (MICREL INC) 5V/3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY PDF資料下載
參數(shù)資料
| 型號： | SY87701VZHTR |
| 廠商： | MICREL INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 5V/3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, LEAD FREE, SOIC-28 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大小： | 161K |
| 代理商： | SY87701VZHTR |
SY87701V
3
Micrel, Inc.
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTIONS
INPUTS
RDINP, RDINN [Serial Data Input]
Differential PECL.
These built-in line receiver inputs are connected to the
differential receive serial data stream. An internal receive
PLL recovers the embedded clock (RCLK) and data
(RDOUT) information. The incoming data rate can be within
one of eight frequency ranges depending on the state of
the FREQSEL pins. See “Frequency Selection” Table.
REFCLK [Reference Clock]
TTL Input.
This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN inputs.
CD [Carrier Detect]
PECL Input.
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW the
data on the inputs RDIN will be internally forced to a constant
LOW, the data outputs RDOUT will remain LOW, the Link
Fault Indicator output LFIN forced LOW and the clock
recovery PLL forced to lock onto the clock frequency
generated from REFCLK.
FREQSEL1, ..., FREQSEL3 [Frequency Select]
TTL
Inputs.
These inputs select the output clock frequency range as
shown in the
“Frequency Selection”
Table.
DIVSEL1, DIVSEL2 [Divider Select]
TTL Inputs.
These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in the
“Reference Frequency Selection”
Table.
CLKSEL [Clock Select]
TTL Input.
This input is used to select either the recovered clock of
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs.
OUTPUTS
LFIN [Link Fault Indicator]
TTL Output.
This output indicates the status of the input data stream
RDIN. Active HIGH signal is indicating when the internal
clock recovery PLL has locked onto the incoming data
stream. LFIN will go HIGH if CD is HIGH and RDIN is within
the frequency range of the Receive PLL (1000ppm). LFIN
is an asynchronous output.
RDOUTP, RDOUTN [Receive Data Output]
Differential
PECL.
These ECL 100K outputs (+3.3V or +5V referenced)
represent the recovered data from the input data stream
(RDIN). This recovered data is sampled on the rising edge
of RCLK.
RCLKP, RCLKN [Clock Output]
Differential PECL.
These ECL 100K outputs (+3.3V or +5V referenced)
represent the recovered clock used to sample the recovered
data (RDOUT).
TCLKP, TCLKN [Clock Output]
Differential PECL.
These ECL 100K outputs (+3.3V or +5V referenced)
represent either the recovered clock (CLKSEL = HIGH) used
to sample the recovered data (RDOUT) or the transmit clock
of the frequency synthesizer (CLKSEL = LOW).
PLLSP, PLLSN [Clock Synthesis PLL Loop Filter]
External loop filter pins for the clock synthesis PLL.
PLLRP, PLLRN [Clock Recovery PLL Loop Filter]
External loop filter pins for the receiver PLL.
POWER & GROUND
Supply Voltage
(Note 1)
V
CCA
V
CCO
GND
Ground
N/C
No Connect
V
CC
Analog Supply Voltage
(Note 1)
Output Supply Voltage
(Note 1)
Note 1.
V
CC
, V
CCA
, V
CCO
must be the same value.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY877021 | 3.3V 28Mbps-2.5Gbps AnyRate Clock and Data Recovery(用于數(shù)據(jù)傳輸速率為28Mbps到2.5Gbps的時鐘恢復(fù)和數(shù)據(jù)重定時電路) |
| SY88713V | 3.3V/5V 622 Mbps PECL LOW-POWER LIMITING POST AMPLIFIER W/PECL SIGNAL DETECT |
| SY88713VKC | 3.3V/5V 622 Mbps PECL LOW-POWER LIMITING POST AMPLIFIER W/PECL SIGNAL DETECT |
| SY88713VKCTR | 3.3V/5V 622 Mbps PECL LOW-POWER LIMITING POST AMPLIFIER W/PECL SIGNAL DETECT |
| SY88713VKG | 3.3V/5V 622 Mbps PECL LOW-POWER LIMITING POST AMPLIFIER W/PECL SIGNAL DETECT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87702L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AnyRate? CDR |
| SY87702L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 28Mbps-2.5Gbps AnyRate CLOCK AND DATA RECOVERY |
| SY87702LHG | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 28Mbps-2.5Gbps AnyRate CLOCK AND DATA RECOVERY |
| SY87702LHGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 28Mbps-2.5Gbps AnyRate CLOCK AND DATA RECOVERY |
| SY87702LHI | 功能描述:IC CLOCK/DATA RECOVERY 64-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:AnyRate® 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。