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參數(shù)資料
| 型號： | SY87701VZHTR |
| 廠商： | MICREL INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 5V/3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, LEAD FREE, SOIC-28 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 161K |
| 代理商： | SY87701VZHTR |
SY87701V
5
Micrel, Inc.
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
CHARACTERISTICS
Performance
The SY87701V PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the Bellcore
Specifications: GR-253-CORE, Issue 2, December 1995 and
ITU-T Recommendations: G.958 document, when used with
differential inputs and outputs.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak-to-peak
amplitude of sinusoidal jitter applied on the input signal that
causes an equivalent 1dB optical/electrical power penalty.
SONET input jitter tolerance requirement condition is the
input jitter amplitude which causes an equivalent of 1dB
power penalty.
Figure 1. Input Jitter Tolerance
OC/STS-N
Level
f0
f1
f2
f3
ft
(Hz)
(Hz)
(Hz)
(kHz)
(kHz)
3
10
30
300
6.5
65
12
10
30
300
25
250
15
1.5
0.40
f0
f1
f2
f4
ft
S
J
(
Frequency
-20dB/decade
-20dB/decade
A
Figure 2. Jitter Transfer
OC/STS-N
Level
fc
P
(kHz)
(dB)
3
130
0.1
12
225
0.1
0.1
-20
fc
Jitter Transfer (dB)
Frequency
-20dB/decade
Acceptable
Range
Jitter Transfer
Jitter transfer function is defined as the ratio of jitter on
the output OC-N/STS-N signal to the jitter applied on the
input OC-N/STS-N signal versus frequency. Jitter transfer
requirements are shown in Figure 2.
Jitter Generation
The jitter of the serial clock and serial data outputs shall
not exceed .01 U.I. rms when a serial data input with no
jitter is presented to the serial data inputs.
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