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參數(shù)資料
| 型號： | SY89221UMG |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 89221 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封裝： | LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 828K |
| 代理商： | SY89221UMG |
Micrel, Inc.
SY89221U
September 2006
4
M9999-092906-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
1, 2
3, 4
15, 16
17, 18
FSELA1, FSELA0
FSELB1, FSELB0
FSELC1, FSELC0
FSELD1, FSELD0
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the four
banks of outputs. Note that each of these inputs is internally connected to a 25k pull-up
resistor and will default to a logic HIGH state if left open. The input-switching threshold is
VCC/2.
5, 8,
11, 14
IN0, /IN0
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the device. They
accept AC- or DC-coupled signals as small as 100mV. The input pairs internally
terminate to a VT pin through 50. Note that these inputs will default to an indeterminate
state if left open. Please refer to the “Input Interface Applications” section for more
details.
6, 12
VT0, VT1
Input Termination Center-Tap: Each side of a differential input pair terminates to a VT
pin. The VT pin provides a center-tap to a termination network for maximum interface
flexibility. See “ Input Interface Applications” section for more details.
7,
13
VREF-AC0,
VREF-AC1
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling
inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with
0.01F low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is
only intended to drive its respective VT pin. Maximum sink/source current is ±1.5mA.
Please refer to the “Input Interface Applications” section for more details.
9
/MR
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously
sets the true outputs LOW, complimentary outputs HIGH, and holds them in that state as
long as /MR remains LOW. This input is internally connected to a 25k pull-up resistor
and will default to logic HIGH state if left open. The input-switching threshold is VCC/2.
10
CLK_SEL
Single-Ended Input: This TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will
default to logic HIGH state if left open. The input-switching threshold is VCC/2.
20, 25, 30, 33,
40
41, 48, 50, 55,
62
VCC
Positive Power Supply. Bypass with a 0.1F||0.01F low ESR capacitor as close to VCC
pin as possible.
21, 22
23, 24
26, 27
28, 29
/QC0, QC0
/QC1, QC1
/QC2, QC2
/QC3, QC3
Bank C LVPECL differential output pairs controlled by FSELC0 and FSELC1. Refer to
“Function Table” for details. Unused output pairs may be left open. Each output is
designed to drive 800mV into 50 terminated to VCC – 2V.
31
NC
No connect.
34, 35,
36, 37
38, 39,
42, 43
44, 45,
46, 47
/QD0, QD0
/QD1, QD1
/QD2, QD2
/QD3, QD3
/QD4, QD4
/QD5, QD5
Bank D LVPECL differential output pairs controlled by FSELD0 and FSELD1. Refer to
“Function Table” for details. Unused output pairs may be left open. Each output is
designed to drive 800mV into 50 terminated to VCC – 2V.
51, 52
53, 54
/QA0, QA0
/QA1, QA1
Bank A LVPECL differential output pairs controlled by FSELA0 and FSELA1. Refer to
“Function Table” for details. Unused output pairs may be left open. Each output is
designed to drive 800mV into 50 terminated to VCC – 2V.
56, 57
58, 59
60, 61
/QB0, QB0
/QB1, QB1
/QB2, QB2
Bank B LVPECL differential output pairs controlled by FSELB0 and FSELB1. Refer to
“Function Table” for details. Unused output pairs may be left open. Each output is
designed to drive 800mV into 50 terminated to VCC – 2V.
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