參數(shù)資料
型號: SY89221UMG
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 89221 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
封裝: LEAD FREE, TQFP-64
文件頁數(shù): 13/17頁
文件大?。?/td> 828K
代理商: SY89221UMG
Micrel, Inc.
SY89221U
September 2006
5
M9999-092906-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description (continued)
Pin Number
Pin Name
Pin Function
64
EN
Single-Ended Input: This TTL/CMOS input disables and enables the outputs. It is
internally connected to a 25k pull-up resistor and will default to logic HIGH state if left
open. When disabled, true outputs go LOW and complementary outputs switches to
HIGH. The input switching threshold is VCC/2. For the input enable and disable functional
description, refer to Figures 2d and 2e.
19, 32, 49, 63
GND,
Exposed Pad
Ground and exposed pad must be connected to the same GND plane on the board.
Function Table
/MR
(1)
EN
(2, 3)
CLK_SEL
FSELx0
(4)
FSELx1
(4)
Q
1
0
IN0÷1
1
0
IN1÷1
1
0
1
0
IN0÷2
1
0
IN1÷2
1
0
X
1
IN0÷4
1
X
1
IN1÷4
1
0
X
0
X
0
Notes:
1.
/MR asynchronously forces Q LOW (/Q HIGH).
2.
EN forces Q LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to “Timing Diagram” section.
3.
EN synchronously enables the outputs between two and six input clock cycles after the rising edge of EN. Refer to “Timing Diagram” section.
4.
FSEL valid for each of the banks A, B, C, and D. Banks can be programmed independent of each other.
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