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參數(shù)資料
| 型號： | SY89538LHY |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 19/23頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTH/FANOUT BUFFER 64-TQFP |
| 標準包裝： | 160 |
| 系列： | Precision Edge® |
| 類型： | 時鐘合成器/扇出緩沖器 |
| PLL： | 是 |
| 輸入： | CMOS，HSTL，LVDS，LVPECL，LVTTL，SSTL，晶體 |
| 輸出： | LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 756MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應商設(shè)備封裝： | 64-EP-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1090 (CN2011-ZH PDF) |
| 其它名稱： | 576-2992 |
Micrel, Inc.
SY89538L
January 2008
M9999-010808-E
hbwhelp@micrel.com or (408) 955-1690
5
Pin Description
Control and Configuration
(continued)
Pin Number
Pin Name
Pin Function
24
26
58
60
PEN0
PEN1
PEN2
PEN3
TTL/CMOS input enable pin. Used to control the PECL POUT0-POUT3 outputs and
as a frequency select pins. PENx, PSELx, and DSEL are used together; see the
“LVPECL Output Post-Divider and Frequency Select Table” for proper decoding.
PENx contains internal 25k pull-up. When disabled, PECL0-PECL3 outputs are a
logic LOW. The threshold voltage VTH = VCC/2.
46
SYNC
TTL/CMOS Output Bank Synchronization Control. Internal 25k pull-up. The default
state is HIGH. After any bank has been programmed, all PECL and LVDS outputs are
synchronized when the SYNC control pin is toggled with a HIGH-LOW-HIGH
transition. See “Synchronization” section for details. The threshold voltage VTH =
VCC/2.
5
FBSEL
TTL/CMOS Input Select Control. Selects either internal or external feedback (zero-delay
function). Internal 25k pull-up. The threshold voltage VTH = VCC/2. Default is logic
HIGH, and selects internal feedback.
Logic HIGH: Internal feedback (from the Programmable Divider)
Logic Low: External feedback (from the FBIN inputs)
28
33
35
PD_4
PD_2
PD_0
TTL/CMOS Programmable Divider-Select Control. Internal 25k pull-down. Default is
logic LOW. The threshold voltage VTH = VCC/2. See “Programmable-Divider Select Table”
for proper decoding.
27
29
34
PD_5
PD_3
PD_1
TTL/CMOS Programmable Divider-Select Control. Internal 25k pull-up. Default is logic
HIGH. The threshold voltage VTH = VCC/2. See “Programmable-Divider Select Table” for
proper decoding.
13, 14
PDSEL1,
PDSEL0
TTL/CMOS Pre-Divider Select Input. Internal 25k pull-up. This two-bit input divider
scales the VCO/2 frequency. See “Pre-Divider Frequency Select Table” for proper
decoding. The threshold voltage VTH = VCC/2.
22
DSEL
TTL/CMOS Post-Divider Option Control. Internal 25k pull-up. Default is logic HIGH.
The threshold voltage VTH = VCC/2.
Logic HIGH: All LVPECL and LVDS outputs operate with their respective output
frequency control (PSELx, PENx, LSEL, LEN).
Logic LOW: Internal PLL is disabled, reference and XTAL signals by-passes the PLL
through a /1, /4, and /16 Post-Divider.
See “LVPECL and LVDS Output Post-Divider and Frequency Select Table” for proper
decoding.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89538LHY TR | 功能描述:時鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Lead Free) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89538LHYTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer |
| SY89538LHZ | 功能描述:時鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Lead Free) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89538LHZ TR | 功能描述:時鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Lead Free) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89538LHZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer |
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