參數(shù)資料
型號: SZA1000
廠商: NXP Semiconductors N.V.
英文描述: QIC digital equalizer
中文描述: QIC磁帶數(shù)字均衡器
文件頁數(shù): 18/32頁
文件大?。?/td> 164K
代理商: SZA1000
1998 Feb 16
18
Philips Semiconductors
Product specification
QIC digital equalizer
SZA1000
C
LOCK FUNCTIONS
Address 37: Main clock divider
Table 27
Clock divider: CLK_DIV; note 1
Note
1.
CD selects the main clock division factor. The CLKIN frequency (pin 6) divided by this factor gives the IC’s operating
frequency f
s
(apart from the WEQ circuit).
D7
D6
D5
D4
D3
D2
D1
D0
CD.2
CD.1
CD.0
Table 28
Clock division factor
CD
CLOCK DIVISION
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
S
TRIPE DETECTOR FUNCTIONS
Address 38: Stripe detector nominal frequency
Table 29
Qualification threshold: STRIPE_F; note 1
Note
1.
SF is an unsigned 5-bit value used to determine the detection threshold for the stripe detector. The nominal detection
f
3
SF
1
+
(
)
×
frequency is
AUXBUS,
PINS
25
AND
27,
SAMPLE RATE REDUCTION AND STAND
-
BY FUNCTIONS
Address 39: Equalizer mode settings
Table 30
EQ_MODE 1; note 1, see also Tables 31 to 34
Note
1.
R1 selects the filter sample rate reduction factor; STBY1 and STBY2 are the DAC and ADC power on/off switches;
ST selects output signal modes for pins 25 and 27.
D7
D6
D5
D4
D3
D2
D1
D0
SF.4
SF.3
SF.2
SF.1
SF.0
D7
D6
D5
D4
D3
D2
D1
D0
STBY2
ST.3
ST.2
ST.1
ST.0
STBY1
R1
---------------------------------
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