參數(shù)資料
型號: SZA1000
廠商: NXP Semiconductors N.V.
英文描述: QIC digital equalizer
中文描述: QIC磁帶數(shù)字均衡器
文件頁數(shù): 24/32頁
文件大小: 164K
代理商: SZA1000
1998 Feb 16
24
Philips Semiconductors
Product specification
QIC digital equalizer
SZA1000
f
3dB(cutoff)(LPF)
3dB cut-off frequency,
analog LPF (DAC filter)
comparator common mode
voltage
comparator input resistance
comparator offset voltage
note 2
8
MHz
V
CM(COMP)
note 3
1.0
1.16
1.4
V
R
i(COMP)
V
IO(COMP)
note 4
note 4
17
26
35
45
k
mV
Serial interface
f
clk(SIO)
t
su(D-CLK)
t
h(D-CLK)
t
d(1)
t
d(2)
t
su(EN-CLK)
t
h(EN-CLK)
serial i/f clock
set-up time: data-to-clock
hold time: data-to-clock
delay clock: new data
delay clock: old data
set-up time: enable-to-clock
hold time: enable-to-clock
10
t
s
+ 10
t
s
t
s
+ 10
t
s
+ 10
1
4
f
s
2t
s
+ 10
MHz
ns
ns
ns
ns
ns
ns
note 5
Digital read section
t
CLKINH
t
CLKINL
t
RDL
t
su(SRD-RRC)
CLKIN HIGH time
CLKIN LOW time
RD LOW time
set-up time: SRD-to-RRC
15
15
t
s
t
CLKINL
5
0.2C
o(L)(SRD)
t
CLKINH
2
0.2C
o(L)(RRC)
t
CLKINL
5
0.2C
o(L)(RRC)
2t
s
+ 10
t
CLKINL
+ 2
0.2C
o(L)(RRC)
ns
ns
ns
ns
note 6
t
h(SRD-RRC)
hold time: SRD-to-RRC
note 6
ns
t
RRCL
RRC LOW time
note 6
t
CLKINL
ns
t
su(AUX-CLKIN)
input set-up time:
AUXBUS-to-CLKIN (pin 6)
input hold time:
AUXBUS-to-CLKIN (pin 6)
PACLK HIGH time
ns
t
h(AUX-CLKIN)
ns
t
PACLKH
note 7
t
CLKINH
2
0.2C
o(L)(PACLK)
t
CLKINL
5
0.2C
o(L)(PACLK)
t
CLKINH
ns
t
PACLKL
PACLK LOW time
note 7
t
CLKINL
ns
t
d(AUX-PACLK)
delay:
AUXBUS-to-PACLK (pin 29)
delay: PACLK to AUXBUS
note 8
10 +
0.2C
o(L)(AUX)
5 +
0.2C
o(L)(PACLK)
ns
t
d(PACLK-AUX)
notes 7 and 8
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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