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參數(shù)資料
| 型號： | T4260ILS |
| 廠商： | ATMEL CORP |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | AUDIO TUNER, PDSO44 |
| 封裝： | SSO-44 |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 299K |
| 代理商： | T4260ILS |
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20
T4260
4528I–AUDR–08/04
DAC1, 2 (Pins 1, 2)
For automatic tuner alignment, the DAC1 and DAC2 of the IC can be controlled by set-
ting gain and offset values. The principle of the operation is shown in Figure 7. The gain
is in the range of 0.67
× V
TUNE to 2.09 × VTUNE. The offset range is +0.98 V to -0.98 V.
For alignment, DAC1 and DAC2 are connected to the varicaps of the preselection filter
and the IF filter. For alignment, offset and gain are set for having the best tuner tracking.
Figure 7. Block Diagram of DAC1, 2
The gain of DAC1 and DAC2 has a range of approximately 0.67
× V(TUNE) to
2.09
× V(TUNE). This range is divided into 255 steps. One step is approximately
(2.09 - 0.67)/255 = 0.00557
× V(TUNE). The gain of DAC1 can be controlled by the bits
38 to 45 (20 to 27) and the gain of DAC2 can be controlled by the bits 66 to bit 73
(20 to 27) as given in Table 26.
Note:
Offset = 64 (intermediate position)
Table 25. Oscillator Operating Modes
Oscillator
Oscillator Buffer
AMLF (Pin 17)
B65
B64
OFF
INPUT
INPUT f. DAC’s
0
X
ON
OFF
AMLF (standard)
1
0
ON
OUTPUT
AMLF (standard)
1
Table 26. Gain of DAC1, 2
Gain DAC1
Approximately
B45
B44
B43
B42
B41
B40
B39
B38
Decimal Gain
Gain DAC2
Approximately
B73
B72
B71
B70
B69
B68
B67
B66
Decimal Gain
0.6728
× V(TUNE)
0
0.6783
× V(TUNE)
0
1
0.6838
× V(TUNE)
0
1
0
2
0.6894
× V(TUNE)
0
1
3
...
0.9959
× V(TUNE)
0
1
0
1
0
58
...
2.0821
× V(TUNE)
1
0
1
253
2.0877
× V(TUNE)
1
0
254
2.0932
× V(TUNE)
1
255
VTUNE
Offset
Gain
DAC1, 2
+/-
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