參數(shù)資料
型號(hào)： T4260ILS
廠商： ATMEL CORP
元件分類： 調(diào)諧器
英文描述： AUDIO TUNER, PDSO44
封裝： SSO-44
文件頁數(shù)： 14/30頁
文件大小： 299K
代理商： T4260ILS
21
T4260
4528I–AUDR–08/04
The offset of DAC1 and DAC2 has a range of approximately +0.98 V to -0.99 V. This
range is divided into 127 steps. One step is approximately 1.97 V/127 = 15.52 mV. The
offset of DAC1 can be controlled by the bits 24 to bit 30 (20 to 26) and the offset gain of
DAC2 can be controlled by the bits 52 to bit 58 (20 to 26) as given in Table 27.
Note:
Gain = 58 (intermediate position)
Permitted DAC Conditions
The internal operation amplifier of the DACs should not operate with a too high internal
difference voltage at their inputs. This means that a voltage difference higher than 0.5 V
at the internal OP input should be avoided in operation mode. The respective output OP
in the DAC is necessary for the addition and amplification of the tuning voltage (at
pin 18) with the desired voltage gain and offset value.
If the tuning voltage reaches a high value e.g. 9 V, with a gain setting of 2 times VTUNE
and an offset of +1 V, then the output OP of the DAC should reach the (calculated) volt-
age of 19 V. The supply voltage of e.g. 10 V, however, limits the output voltage (of the
DAC) to 10 V maximum.
Due to the (limiting) supply voltage and the internal gain resistance ratio of 6, the miss-
ing 9 V (calculated voltage - V
s) cause a voltage of 1.5 V at the OP input. This condition
may not remain for a longer period of time.
As long as the calculated DAC output voltage value does not exceed the supply voltage
value by more than 3 V, no damages should occur during the product’s lifetime as the
input voltage of the internal OP input voltage does not exceed 0.5 V.
VTUNE x DAC gain factor + DAC offset < V
S + 3 V
(9 V x 2 + 1 V) < 10 V + 3 V (condition not allowed)
This means when having a gain factor of 2 and an offset value of 1 V, the tuning voltage
should not exceed 6 V.
Maximum tuning voltage < (V
S + 3 V - DAC offset)/DAC gain factor
e.g.: maximum tuning voltage = (10 V + 3 V - 1 V)/2 = 6 V
It is also possible to reduce the gain or the offset value instead of (or along with) the tun-
ing voltage.
Table 27. Offset of DAC1, 2
Offset DAC1
Approximately
B30
B29
B28
B26
B25
B24
Decimal Offset
Offset DAC2
Approximately
B58
B57
B56
B55
B54
B53
B52
Decimal Offset
0.9815 V
0
0.9659 V
0
1
0.9512 V
0
1
0
2
0.9353 V
0
1
3
...
-0.0120 V
1
0
64
...
-0.9576 V
1
0
1
125
-0.9733 V
1
0
126
-0.9890 V
1
127
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