參數(shù)資料
型號: T4260ILS
廠商: ATMEL CORP
元件分類: 調(diào)諧器
英文描述: AUDIO TUNER, PDSO44
封裝: SSO-44
文件頁數(shù): 17/30頁
文件大?。?/td> 299K
代理商: T4260ILS
24
T4260
4528I–AUDR–08/04
There are also two HCDEL registers (for the high current CP delay time) but only one of
them is active. One of the HCDEL registers can be activated by bit 18. The delay time of
the HCDEL register can be selected with bit 20 and bit 21 or bit 22 and bit 23). The
current for the high CP (HCCP) can be set by bit 62 and the current for the low current
CP (LCCP) by bit 63.
With bit 145 the AM- or FM-Loopfilter (pin) can be activated. It is also possible to use the
AM-Loopfilter in FM mode (instead of the FM-Loopfilter) or the FM-Loopfilter in AM
mode.
High-speed Tuning
The fractional mode (bit 144 = 0) in connection with the direct shift mode (bit 32 = 0)
al low s ver y fa st f r equ ency ch ang es w i th fo ur tim e s t he st ep fr eq uen cy
(50 kHz = 4
× f
PDF) at low frequency steps (e.g., fPDF = 12.5 kHz). In direct shift mode,
the R- and the N-divider are shifted by 2 bits to the right (this corresponds to a R- and
N-divider division by 4 or a step frequency multiplication by 4).
Due to the 2-bit shift, a faster tuning response time of approximately 1 ms instead of
3-4 ms for a tune over the whole FM band from 87.5 MHz to 108 MHz is possible with
f
PDF =12.5 kHz.
If the FM receiving frequency is 103.2125 MHz (with e.g. f
PDF = 12.5 k Hz a nd
f
IF = 10.7 MHz), an N-divider of 9113 and an R-divider of 12 are necessary when using a
reference-frequency (f
ref) of 150 kHz.
f
VCO = fIF + frec = 10.7 MHz + 103.2125 MHz = 113.9125 MHz
f
PDF = fVCO/N = fref/R = 113.9125 MHz/9113 = 150 kHz/12 = 12.5 kHz
An important condition for the use of the fractional mode is an R-divider with an integer
value after the division by 4 (R-dividers have to be a multiple of 4).
After a 2-bit shift (divider division by 4), the R-divider is now 3 (instead of 12) and the
N-divider is 2278.25 (instead of 9113). The new N-divider of 2278.25 is also called
fractional step because the modulo value of the N-divider is 0.25 = . In total, there are
4 different fractional 2-bit shift steps: full, , and step.
If the fractional mode is switched off (bit 144 = 1) during direct shift mode (bit 32 = 0), the
modulo value of the N-divider will be ignored (the new N-divider is then 2278 instead of
2278.25). This means that the PLL locks on the next lower multiple frequency of 4
× f
PDF
(in our case f
PDF = 12.5 kHz). The new VCO frequency (fVCO) is then 113.9 MHz (instead
of 113.9125 MHz in fractional mode).
Also the PLL has additionally a special fractional logic which allows a good spurious
suppression in the fractional and direct shift mode. Activating the wire switch (bit 60 = 1)
and the correction charge pump (bit 60 = 1) the spurious suppression is active.
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