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參數(shù)資料
| 型號(hào)： | T7503 |
| 元件分類： | Codec |
| 英文描述： | T7503 Dual PCM Codec with Filters |
| 中文描述： | T7503雙PCM編解碼器與濾波器 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 417K |
| 代理商： | T7503 |
Lucent Technologies Inc.
3
Data Sheet
February 1998
T7503 Dual PCM Codec with Filters
Pin Information
(continued)
* I
d
indicates a pull-down device is included on this lead.
Table 1. Pin Descriptions
Symbol
VF
X
VF
X
VF
X
VF
X
GS
GS
VF
R
OP1
VF
R
OP0
VF
R
ON1
VF
R
ON0
V
DD
Pin
17
4
16
5
15
6
20
1
19
2
8
Type
I
Name/Function
IN1
IN0
IP1
IP0
1
X
0
Voice Frequency Transmitter Negative Input.
uncommitted operational amplifier at the transmit filter input.
Voice Frequency Transmitter Positive Input.
uncommitted operational amplifier at the transmit filter input.
Gain Set for Transmitter.
Output of the transmit uncommitted operational amplifi-
er. The pin is the input to the transmit differential filters.
Voice Frequency Receiver Positive Output.
loads.
Voice Frequency Receiver Negative Output.
er) loads.
+5 V Power Supply
. This pin should be bypassed to analog ground with at least
0.1
μ
F of capacitance as close to the device as possible. V
and digital internal circuits.
Analog Grounds
. Both ground pins must be connected on the circuit board. AGND
serves both analog and digital internal circuits.
Receive PCM Data Input
. The data on this pin is shifted into the device on the fall-
ing edges of MCLK. Sixteen consecutive bits of data (8 bits for channel 0, and
8 bits for channel 1) are entered after the FS pulse has been detected.
Transmit PCM Data Output
. This pin remains in the high-impedance state except
during active transmit time slots. Sixteen consecutive bits of data (8 bits for channel
0 and 8 bits for channel 1) are shifted out on the rising edge of MCLK. Data is shift-
ed out on the rising edge of MCLK.
Master Clock Input
. The frequency must be 2.048 MHz or 4.096 MHz. This clock
serves as the bit clock for all PCM data transfer. A 40% to 60% duty cycle is re-
quired.
Digital Ground
. Ground connection for the digital circuitry.
Frame Sync
. This signal is an edge trigger and must be high for a minimum of one
MCLK cycle. This signal must be derived from MCLK. If FS is low for 500
MCLK remains active, then the device fully powers down. An internal pull-down de-
vice is included on FS.
Voltage Common Mode
. 2.4 Vdc.
Analog
inverting input to the
I
Analog
noninverting input to the
X
O
O
This pin can drive 300
(or greater)
O
This pin can drive 300
(or great-
—
DD
serves both analog
GNDA1
GNDA0
D
18
3
12
—
R
I
D
X
11
O
MCLK
9
I
GNDD
FS
10
13
—
I
d
*
μ
s while
VCM0
VCM1
7
14
O
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