- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371180 > T8532 T8502 and T8503 Dual PCM Codecs with Filters PDF資料下載
參數(shù)資料
| 型號： | T8532 |
| 元件分類： | Codec |
| 英文描述： | T8502 and T8503 Dual PCM Codecs with Filters |
| 中文描述： | T8502和T8503雙的PCM編解碼器與濾波器 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 999K |
| 代理商： | T8532 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
Lucent Technologies Inc.
21
Preliminary Data Sheet
November 2000
Codec Chip Set
T8531/T8532 Multichannel Programmable
Chip Set Functional Description
(continued)
T8531 Reset and Start-Up
(continued)
Internal Reset
Internal reset is defined as the process that starts when
the internal reset line is brought low. This happens as a
consequence of hardware (RTSB) or software (BCW1)
reset. The internal reset process performs the following
functions:
1. The frequency synthesizer does not receive any
reset signal, and is thus unaffected by reset. Follow-
ing power-on reset of the T8531, the frequency syn-
thesizer takes the mode determined by the
SCKSEL pin.
2. The T8531 custom logic jams all resettable latches,
counters, and registers to their default values. No
data is latched on any of the T8531 interfaces during
internal reset.
3. The DSP engine is held in reset state.
4. The internal reset line is held low for a minimum of
18 ms to allow the frequency synthesizer to reach its
final accuracy. An internal counter is started when
the internal reset line goes low. It counts 80 frame
sync pulses on SFS before releasing the internal
reset line.
5. When the internal reset line goes high and the EXM
(internal) signal is held low, the DSP engine begins
its start-up routine by fetching the first instruction
from location 0 of the internal ROM.
6. At the rising edge of the internal reset line, all the
T8531 custom logic blocks commence their normal
operation.
Reset of the T8532 Devices
There are two options for reset of the T8532 chips.
The T8532s can make use of the same hardware reset
pulse as the T8531. The T8531 supplies OSCK to the
T8532s as soon as it is available, i.e., before the hard-
ware reset has gone away. It is recommended that
hardware reset be applied to all chips simultaneously.
Alternatively, the T8532s can be reset through software
reset (Tables 21 and 22), which is generated by the
external controlling device and routed to the T8532s
via the T8531. This can only occur when OSCK is
guaranteed to be valid, i.e., not within 10 ms of power-
on hardware reset.
Start-Up After Internal Reset
There is a specific sequence of microprocessor inter-
face instructions that must be followed after internal
reset in order to properly configure the T8531 and
T8532s for normal operation.
1. If nondefault values are required, the T8531 board
control word 1 (address 0x1FFE) must be updated.
2. The 16 TSA RAM locations must be written before
0x1FFC. CTZ must be disabled (see Table 20B).
3. The all channel test register must be set for normal
operation (addresses 0x1510 and 0x1550 set to
0x0004).
4. The T8531 control registers must be set. All 16
channels must be powered up (addresses
0x1500—0x1507 and 0x1540—0x1547 must be set
to 0x8000).
5. The amplitude of the calibration sine wave must be
set by writing address 0x0580 to coefficient
0xAA20, and address 0x0581 to coefficient
0xF49D.
6. All 16 channels must be put into initialization mode
(addresses 0x1518—0x151F and 0x1558—0x155F
must be set to 0x0080).
7. The DSP engine RAM address 0x0002 must be set
to 0x0700 to begin the first part of the T8532 cali-
bration start-up sequence.
8. After 70 ms, all 16 T8532 channels must be put into
loopback mode (addresses 0x1508—0x151F and
0x1548—0x154F must be set to 0x8001).
9. The DSP engine RAM address 0x0002 must be set
to 0x0720 to begin the second part of the T8532
calibration start-up sequence.
10. After 70 ms, both T8532s should be sent a soft
reset (addresses 0x1517 and 0x1557 set to
0x8000) and the all channel test register should be
set for normal operation (addresses 0x1510 and
0x1550 set to 0x0004). Normal T8531 operation
commences with the next SFS frame sync. The
chips are now ready for channels to be enabled and
filter coefficients to be set.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T8533 | T8533/34 Quad Programmable Line Card Signal Processor |
| T8534 | T8533/34 Quad Programmable Line Card Signal Processor |
| T8535B | T8535B/T8536B Quad Programmable Codec |
| T8536B | T8535B/T8536B Quad Programmable Codec |
| T8538B | T8538B Quad Programmable Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T8533 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor |
| T85331G | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T85331J | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T8534 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor |
| T8535B | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8535B/T8536B Quad Programmable Codec |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。