參數(shù)資料
型號(hào): T8536B
元件分類: Codec
英文描述: T8535B/T8536B Quad Programmable Codec
中文描述: T8535B/T8536B四可編程編解碼器
文件頁數(shù): 34/50頁
文件大小: 929K
代理商: T8536B
34
Agere Systems Inc.
Preliminary Data Sheet
September 2001
T8535B/T8536B Quad Programmable Codec
Timing Characteristics
Control Interface Timing
Serial Control Port Timing
Table 17. Serial Control Port Timing
(See Figures 22 and 23.)
* The t
SXBDLY
delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte.
Symbol
f
DCLK
t
CSSETUP
t
CSHOLD
t
SXDLY
t
SDHOLD
t
SDSETUP
t
SDZ
t
RISE
t
FALL
t
RISE
,
t
FALL
t
CSBHOLD
t
SXBDLY
t
CSBSETUP
Chip Select Setup Time, Byte-by-Byte Mode
t
SDBHOLD
Data Hold Time, Byte-by-Byte Mode
t
SDBSETUP
Data Setup Time, Byte-by-Byte Mode
Parameter
Test Conditions
D
CLK
= 4.096 MHz
D
CLK
= 4.096 MHz
D
CLK
= 4.096 MHz
D
CLK
= 4.096 MHz
D
CLK
= 4.096 MHz
D
CLK
= 4.096 MHz
D
CLK
= 4.096 MHz
D
CLK
= 4.096 MHz
I
L
= 15 mA,
C
LOAD
= 100 pF
D
CLK
= 4.096 MHz
D
CLK
= 4.096 MHz*
D
CLK
= 4.096 MHz
D
CLK
= 4.096 MHz
D
CLK
= 4.096 MHz
Min
7
4
4
7
100
Typ
Max
4096
9
12
12
30
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Frequency (all commands)
Chip Select Setup Time, Normal Mode
Chip Select Hold Time, Normal Mode
Output Data Delay, Normal Mode
Input Data Hold Time, Normal Mode
Input Data Setup Time, Normal Mode
Output Data, High Impedance
Clock Edge Rise Time
Clock Edge Fall Time
Line Driver Rise/Fall Time (DO output)
Chip Select Hold Time, Byte-by-Byte Mode
Output Data Delay, Byte-by-Byte Mode
4
7
4
7
9
ns
ns
ns
ns
ns
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