參數(shù)資料
型號(hào)： T8536B
元件分類： Codec
英文描述： T8535B/T8536B Quad Programmable Codec
中文描述： T8535B/T8536B四可編程編解碼器
文件頁(yè)數(shù)： 4/50頁(yè)
文件大?。?/td> 929K
代理商： T8536B
4
Agere Systems Inc.
Preliminary Data Sheet
September 2001
T8535B/T8536B Quad Programmable Codec
General Description
Refer to Figure 1 for the following discussion.
5-8125aF
* Second PCM port not available in all package types.
Figure 1. Functional Block Diagram, Each Section
RST
SLIC
TO/FROM
ANALOG
GAIN
A/D
CONVERTER
ANALOG
BUFFER
D/A
CONVERTER
D
L
A
L
D
L
TERMINATION
IMPEDANCE
HYBRID
BALANCE
NETWORK
DIGITAL GAIN
(GAIN TRANSFER)
μ
-LAW
OR
A-LAW
CHPER
COMMON
A
L
D
L
PCM BUS
INTERFACE
DX0
DX1*
TSX0*
TSX1*
DR1*
TO/FROM
PCM BUS
POWER AND
GROUND
18
FS
BCLK
SLIC
CONTROL LATCHES
MICROPROCESSOR CONTROL
CONTROL AND DATA SIGNALS
4
SERIAL CONTROL INTERFACE
PER
CHANNEL
COMMON
0 TO 6
FREQUENCY
SYNTHESIZER
0 TO 3
FILTER
CONVERSION
DIGITAL GAIN
(GAIN TRANSFER)
DR0
VF
R
OPn
VF
R
ONn
VF
X
In
This device performs virtually all the signal processing
functions associated with a central office line termina-
tion. Functionality includes line termination impedance
synthesis, fixed hybrid balance impedance synthesis,
and level conversion both in the analog sense to
accommodate various subscriber line interface circuits
(SLICs) and in the digital sense for adjustment of the
levels on the PCM bus. In general, the termination
impedance synthesis generates the equivalent of a cir-
cuit with the parallel combination of a capacitor and a
resistor in series with a resistor, or the parallel combi-
nation of a resistor and the series combination of a
resistor and capacitor. These general forms of imped-
ance characteristics will satisfy most of the require-
ments specified throughout the world. Programmable
selection of either
μ
-law or A-law encoding further aids
worldwide deployment. All coefficients used in the filter-
ing algorithms can be computed off-line in advance and
downloaded to the device at the time of powerup. All
signal processing is contained within the device, and
there are only three interfaces of consequence to the
system designer: the SLIC interface, the PCM inter-
face, and the control interface.
The SLIC interface is designed to be flexible and con-
venient to use with a variety of SLIC circuits. With an
appropriate choice of SLIC, no external components
are required in the interface, with the exception of a dc
blocking capacitor in the transmit direction. In some
cases, dc blocking capacitors in the receive direction
may be necessary as well, since the device operates
from a single low-voltage supply.
The PCM bus interface is flexible in that it allows, inde-
pendently, the transmit and receive data for any chan-
nel to be placed in any time slot. The bus can be
operated at a maximum 16.384 Mbits/s rate to accom-
modate a maximum 256 time slots. Separate pins
are provided for each direction of transmission to
allow 4-wire bus operation. The frame strobe signal is
an 8 kHz signal that defines the beginning of the frame
structure for all four channels. The interface will count
8 bits per time slot and insert or read the data for each
channel as programmed. Lower speeds of the PCM
bus are allowed. The PCM clock must be synchronous
with the frame strobe signal.
The microprocessor control interface is a serial inter-
face that uses the classical chip select type of opera-
tion. The interface controls the device by writing or
reading various internal addresses. The command set
consists of simple read and write operations, with the
address determining the effect. All the memory loca-
tions, including the per-chip functions, are organized by
channel.
There are several test modes included to facilitate con-
firmation of correct operation. In the signal path, two
analog and three digital loopback tests are available,
while in the microprocessor interface, there is a write/
read test mode that tests the operation of the memory.
Use of external test access switches allows a complete
test of the signal path through the line card so that cor-
rect operation of various operational modes can be ver-
ified.
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