參數(shù)資料
型號(hào): T89C51CC01UA-RLTIM
廠商: Atmel
文件頁(yè)數(shù): 113/123頁(yè)
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K 44VQFP
標(biāo)準(zhǔn)包裝: 160
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤(pán)
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC01UARLTIM
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5
A/T89C51CC01
4129N–CAN–03/08
Figure 2. Port 0 Structure
Notes:
1. Port 0 is precluded from use as general-purpose I/O Ports when used as
address/data bus drivers.
2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only.
Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.
Figure 3. Port 2 Structure
Notes:
1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus
drivers.
2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for
memory bus cycle.
When Port 0 and Port 2 are used for an external memory cycle, an internal control signal
switches the output-driver input from the latch output to the internal address/data line.
Read-Modify-Write
Instructions
Some instructions read the latch data rather than the pin data. The latch based instruc-
tions read the data, modify the data and then rewrite the latch. These are called "Read-
Modify-Write" instructions. Below is a complete list of these special instructions (see
Table ). When the destination operand is a Port or a Port bit, these instructions read the
latch rather than the pin:
D
Q
P0.X
LATCH
INTERNAL
WRITE
TO
LATCH
READ
PIN
READ
LATCH
0
1
P0.x (1)
ADDRESS LOW/
DATA
CONTROL
VDD
BUS
(2)
D
Q
P2.X
LATCH
INTERNAL
WRITE
TO
LATCH
READ
PIN
READ
LATCH
0
1
P2.x (1)
ADDRESS HIGH/ CONTROL
BUS
VDD
INTERNAL
PULL-UP (2)
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