參數(shù)資料
型號: T89C51CC01UA-RLTIM
廠商: Atmel
文件頁數(shù): 61/123頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K 44VQFP
標準包裝: 160
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC01UARLTIM
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 151
dsPIC33F
For example, suppose a 10 MHz crystal is being used,
with “XT with PLL” being the selected oscillator mode.
If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO
input of 10/2 = 5 MHz, which is within the acceptable
range of 0.8-8 MHz. If PLLDIV<8:0> = 0x1E, then
M = 32. This yields a VCO output of 5 x 32 = 160 MHz,
which is within the 100-200 MHz ranged needed.
If PLLPOST<1:0> = 0, then N2 = 2. This provides a
Fosc of 160/2 = 80 MHz. The resultant device operating
speed is 80/2 = 40 MIPS.
EQUATION 8-3:
XT WITH PLL MODE
EXAMPLE
FIGURE 8-2:
dsPIC33F PLL BLOCK DIAGRAM
TABLE 8-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
FCY =
FOSC
=
1 (10000000*32) = 40 MIPS
2
2*2
Oscillator Mode
Oscillator Source
POSCMD<1:0>
FNOSC<2:0>
Note
Fast RC Oscillator with Divide-by-N
(FRCDIVN)
Internal
11
111
1, 2
Fast RC Oscillator with Divide-by-16
(FRCDIV16)
Internal
11
110
1
Low-Power RC Oscillator (LPRC)
Internal
11
101
1
Secondary (Timer1) Oscillator (SOSC)
Secondary
11
100
1
Primary Oscillator (HS) with PLL
(HSPLL)
Primary
10
011
Primary Oscillator (XT) with PLL
(XTPLL)
Primary
01
011
Primary Oscillator (EC) with PLL
(ECPLL)
Primary
00
011
1
Primary Oscillator (HS)
Primary
10
010
Primary Oscillator (XT)
Primary
01
010
Primary Oscillator (EC)
Primary
00
010
1
Fast RC Oscillator with PLL (FRCPLL)
Internal
11
001
1
Fast RC Oscillator (FRC)
Internal
11
000
1
Note 1:
OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2:
This is the default oscillator mode for an unprogrammed (erased) device.
0.8-8.0 MHz
Here
100-200 MHz
Here
Divide by
2, 4, 8
Divide by
2-513
Divide by
2-33
1.6-16.0 MHz
Source (Crystal, External Clock
PLLPRE
XVCO
PLLDIV
PLLPOST
or Internal RC)
Here
12.5-80 MHz
Here
FOSC
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