參數(shù)資料
型號: T89C51CC01UA-RLTIM
廠商: Atmel
文件頁數(shù): 27/123頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K 44VQFP
標(biāo)準(zhǔn)包裝: 160
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC01UARLTIM
PIC18F2XK20/4XK20
DS41303G-page 122
2010 Microchip Technology Inc.
TABLE 10-1:
PORTA I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
Type
Description
RA0/AN0/C12IN0-
RA0
0
O
DIG
LATA<0> data output; not affected by analog input.
1
I
TTL
PORTA<0> data input; disabled when analog input enabled.
AN0
1
I
ANA
ADC input channel 0. Default input configuration on POR; does not
affect digital output.
C12IN0-
1
I
ANA
Comparators C1 and C2 inverting input, channel 0. Analog select is
shared with ADC.
RA1/AN1/C12IN1-
RA1
0
O
DIG
LATA<1> data output; not affected by analog input.
1
I
TTL
PORTA<1> data input; disabled when analog input enabled.
AN1
1
I
ANA
ADC input channel 1. Default input configuration on POR; does not
affect digital output.
C12IN1-
1
I
ANA
Comparators C1 and C2 inverting input, channel 1. Analog select is
shared with ADC.
RA2/AN2/C2IN+
VREF-/CVREF
RA2
0
O
DIG
LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
1
I
TTL
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2
1
I
ANA
ADC input channel 2. Default input configuration on POR; not affected
by analog output.
C2IN+
1
I
ANA
Comparator C2 non-inverting input. Analog selection is shared with
ADC.
VREF-
1
I
ANA
ADC and comparator voltage reference low input.
CVREF
x
O
ANA
Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/C1IN+/
VREF+
RA3
0
O
DIG
LATA<3> data output; not affected by analog input.
1
I
TTL
PORTA<3> data input; disabled when analog input enabled.
AN3
1
I
ANA
A/D input channel 3. Default input configuration on POR.
C1IN+
1
I
ANA
Comparator C1 non-inverting input. Analog selection is shared with
ADC.
VREF+
1
I
ANA
ADC and comparator voltage reference high input.
RA4/T0CKI/C1OUT
RA4
0
O
DIG
LATA<4> data output.
1
I
ST
PORTA<4> data input; default configuration on POR.
T0CKI
1
I
ST
Timer0 clock input.
C1OUT
0
O
DIG
Comparator 1 output; takes priority over port data.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
0
O
DIG
LATA<5> data output; not affected by analog input.
1
I
TTL
PORTA<5> data input; disabled when analog input enabled.
AN4
1
I
ANA
A/D input channel 4. Default configuration on POR.
SS
1
I
TTL
Slave select input for SSP (MSSP module).
HLVDIN
1
I
ANA
Low-Voltage Detect external trip point input.
C2OUT
0
O
DIG
Comparator 2 output; takes priority over port data.
OSC2/CLKOUT/
RA6
0
O
DIG
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1
I
TTL
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes
only.
OSC2
x
O
ANA
Main oscillator feedback output connection (XT, HS and LP modes).
CLKOUT
x
O
DIG
System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator
modes.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
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