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參數(shù)資料
| 型號： | TAS3004PFBRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 42/84頁 |
| 文件大?。?/td> | 671K |
| 代理商： | TAS3004PFBRG4 |
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7–2
Clears all the registers in the circuits
Purges the codec
Selects analog input A (RINA and LINA) and sets the input A active indicator (INPA) low.
Initializes the equalization parameters to AllPass filters
Sets the digital audio interface to I2S—18-bit mode
Sets the bass/treble to 0 dB
Sets the mixer gain to 0 dB SDIN1 and mutes both SDIN2 and analog-in
Sets the volume to –40 dB
Turns off all enhancement features (DRCE, etc.).
Reads the I2C address. If the address is 68h, the device reads its EPROM. It is possible to load the
user-defined bass/treble data and break points (optional). If there is no data, the device loads default
bass/treble delta and break points from ROM.
If the address is 6Ah, the device puts the I2C interface in slave mode and waits for input.
7.2.3
Reset Circuit
Since the TAS3004 device has an internal power-on reset (POR), in many cases, additional components are not
needed to reset the device. It resets internally at approximately 80% of VDD.
In the case where the system’s power supplies are slow in reaching their final voltage or where there is a difference
in the time the system power supplies take to become stable, the TAS3004 reset can be delayed by a simple RC
circuit.
0.1
F
DVDD
6
TAS3004
RESET
10 k
DVSS
Figure 7–1. TAS3004 Reset Circuit
The values for the above circuit can be calculated by the simple equation:
trd = 0.8RC + 400 s
Where:
trd = The delay before the TAS3004 device comes out of reset
C = Value of the capacitance from RESET (pin 6) to DVSS
R = Value of the resistance from RESET (pin 6) to DVDD
The circuit described in Figure 7–1 delays the start-up of the TAS3004 device approximately 1.2 ms.
When it is necessary to control the reset of the TAS3004 device with an external device, such as a microcontroller,
RESET (pin 6) can be treated as a logic signal. It then brings the device out of reset when the voltage on RESET
reaches VDD/2.
7.2.4
Fast Load Mode
While in fast load mode, it is possible to update the parametric equalization without any audio processing delay. The
audio processor pauses while the RAM is updated in this mode. Bass and treble cannot download in this mode. Mixer1
and Mixer2 registers can download in this mode or normal mode (FL bit = 0).
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