參數(shù)資料
型號(hào)： TAS3004PFBRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： GREEN, PLASTIC, TQFP-48
文件頁數(shù)： 6/84頁
文件大?。?/td> 671K
代理商： TAS3004PFBRG4
2–1
2 Audio Data Formats
2.1
Serial Interface Formats
The TAS3004 device works in master or slave mode.
In the master mode, terminal 21 (IFM/S) is tied high. This activates the master clock (MCLK) circuitry. A crystal can
be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be
connected to XTALI/MCLK. In that case, MCLK outputs from terminal 12 (MCLKO) with terminals 19 (LRCLK/O) and
20 (SCLK/O) becoming outputs to drive slave devices.
In the slave mode, IFM/S is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device
requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options
for selecting the clock rates. If the 512fS MCLK rate is selected, terminal 11 (CLKSEL) is tied high and an MCLK rate
of 512fS must be supplied. If the 256fS MCLK is selected, CLKSEL is tied low and an MCLK of 256fS must be supplied.
In both cases, an LRCLK of 64SCLK must be supplied.
MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.
If the LRCLK phase changes more than 10MCLK, the codec automatically resets.
The TAS3004 device is compatible with 13 different serial interfaces. Available interface options are I2S, right justified,
and left justified. Table 2–1 indicates how the 13 options are selected using the I2C bus and the main control register
(MCR, I2C address x01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64fS.
Additionally, the 16-bit mode operates at 32fS.
Table 2–1. Serial Interface Options
MODE
MCR BIT (6)
MCR BIT (5–4)
MCR BIT (1–0)
SERIAL INTERFACE
SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0
0
00
16-bit, left justified, 32fS
1
00
16-bit, left justified, 64fS
2
1
01
00
16-bit, right justified, 64fS
3
1
10
00
16-bit, I2S, 64fS
4
1
00
01
18-bit, left justified, 64fS
5
1
01
18-bit, right justified, 64fS
6
1
10
01
18-bit, I2S, 64fS
7
1
00
10
20-bit, left justified, 64fS
8
1
01
10
20-bit, right justified, 64fS
9
1
10
20-bit, I2S, 64fS
10
1
00
11
24-bit, left justified, 64fS
11
1
01
11
24-bit, right justified, 64fS
12
1
10
11
24-bit, I2S, 64fS
Figure 2–1 through Figure 2–9 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the
different interface protocols.
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