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參數(shù)資料
| 型號(hào)： | TAS3103IDCP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封裝： | PLASTIC, HTSSOP-38 |
| 文件頁(yè)數(shù)： | 91/148頁(yè) |
| 文件大小： | 1247K |
| 代理商： | TAS3103IDCP |
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Table 22. TAS3103 Clock Default Settings
CLOCK
DEFAULT SETTING
SCLKOUT1
SCLKIN
SCLKOUT2
SCLKIN
LRCLK
Input
MCLKO
MCLKI or XTALI
DAP processing clock
Set by pins PLL0 and PLL1
Microprocessor clock
Set by pin MICROCLK_DIV
I2C sampling clock
I2C master mode
Microprocessor clock/4
I2C slave mode
Microprocessor clock/2
I2C master SCL
I2C sampling clock/90
The selections provided by the dedicated TAS3103 input pins and the programmable settings provided by I2C
subaddress commands give the TAS3103 a wealth of clocking options. Table 21, in the section describing the serial
audio port (SAP), lists typical clocking selections for different audio sampling rates. However, the following clocking
restrictions must be adhered to:
MCLKI or XTALI
≥ 128 FS (NOTE: For some TDM modes, MCLKI or XTALI must be ≥ 256 FS)
DAP clock
≥ 1400 x FS
DAP clock < 136 MHz
Microprocessor clock/20
≥ I2C SCL clock
Microprocessor clock
≤ 35 MHz
I2C oversample clock/10
≥ I2C SCL clock
XTALI
≤ 12.288 MHz
MCLKI
≤ 25 MHz, unless PLL is bypassed
As long as these restrictions are met, all other clocking options are allowed.
2.3
Controller
The controller serves as the interface between the digital audio processor (DAP), the asynchronous I2C bus interface,
and the four general-purpose I/O (GPIO) pins. Included in the controller block is an industry-standard 8051
microprocessor and an I2C master/slave bus controller.
2.3.1
8051 Microprocessor
The 8051 microprocessor receives and distributes I2C write data, retrieves and outputs to the I2C bus controller the
required I2C read data, and participates in most processing tasks requiring multiframe processing cycles. The
microprocessor also controls the flow of data into and out of the GPIO pins, which includes volume control when in
the I2C master mode The microprocessor has its own data RAM for storing intermediate values and queuing I2C
commands, and a fixed program ROM. The microprocessor’s program cannot be altered.
2.3.2
I2C Bus Controller
The TAS3103 has a bidirectional, two-wire, I2C-compatible interface. Both 100K-bps and 400K-bps data transfer
rates are supported, and the TAS3103 controller can serve as either a master I2C device or a slave I2C device.
Master/slave operation is defined by the logic level input into pin I2CM_S (logic 1 = master mode, logic 0 = slave
mode).
If this input level is changed, the TAS3103 must be reset.
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