參數(shù)資料
型號: TAS3202PAGR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 5/66頁
文件大?。?/td> 817K
代理商: TAS3202PAGR
23
22
SCLK
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
24-Bit Mode
9
8
5
4
1
0
19
18
20-Bit Mode
5
4
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
23
22
SCLK
32 Clks
Right Channel
9
8
5
4
1
0
19
18
5
4
1
0
1
0
15
14
MSB
LSB
2-Channel I2S (Philips Format) Stereo Input/Output
T0034-04
www.ti.com
SLES208B – JUNE 2009 – REVISED MARCH 2011
Following a reset, ensure that the clock register (0x00) is written before performing volume, treble, or bass
updates.
Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet
operation. However, care must be taken to ensure that the mute command has completed before the SAP
is commanded to reconfigure. Similarly, the TAS3202 should not be commanded to unmute until after the
SAP has completed a reconfiguration. The reason for this is that an SAP configuration change while a
volume or bass or treble update is taking place can cause the update not to be completed properly.
When the TAS3202 is transmitting serial data, it uses the negative edge of SCLK to output a new data bit.
The TAS3202 samples incoming serial data on the rising edge of SCLK.
3.9.1
2-Channel I
2S Timing
In 2-channel I2S timing, LRCLK is LOW when left-channel data is transmitted and HIGH when
right-channel data is transmitted. SCLK is a bit clock running at 64 × fS and clocks in each bit of the data.
There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on
the data lines. The data is written most-significant bit (MSB) first and is valid on the rising edge of the bit
clock. The TAS3202 masks unused trailing data-bit positions.
Figure 3-2. I2S 64fS Format
Copyright 2009–2011, Texas Instruments Incorporated
Physical Characteristics
13
Product Folder Link(s): TAS3202
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