參數(shù)資料
型號(hào)： TAS3202PAGR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 66/66頁(yè)
文件大?。?/td> 817K
代理商： TAS3202PAGR
www.ti.com
SLES208B – JUNE 2009 – REVISED MARCH 2011
TERMINAL
INPUT/
PULLUP/
DESCRIPTION
OUTPUT(1)
PULLDOWN(2)
NAME
NO.
The frequency for this clock is 6.144 MHz/(n+1), where n is
MCLK_OUT2
47
Digital output
programable in the range 0 to 255. Default value is 1.024 MHz. This
output is valid even when reset is LOW.
The frequency for this clock is 512 kHz/(n+1) where n is programmable
MCLK_OUT3
46
Digital output
in the range 0 to 255. Default value is 512 kHz. This output is valid
even when reset is LOW.
This pin can be programmed by the application firmware to mute the
MUTE
5
Digital input
Pulldown
TAS3202. It has no default functionality
20–23,
NC
No connect
29–32
This pin can be programmed by the application firmware to power down
PDN
7
Digital input
the TAS3202. Default operation is to stop the DSP.
RESERVED
50
N/A
Pulldown
Connect to ground.
System reset input, active low. A system reset is generated by applying
RESET
62
Digital input
Pullup
a logic LOW to this terminal.
Requires a 22-k
(1%) external resistor to ground to set analog
REXT
27
Analog output
currents. Trace capacitance must be kept low.
SCLK_IN
59
Digital input
Serial data input bit clock for I2S interface
SCLK_OUT
52
Digital output
Serial data output bit clock for I2S interface
SDIN1/GPIO3
61
Digital I/O
Pullup
Serial data input 1 for I2S interface or programmable for GPIO #3
SDIN2/GPIO4
60
Digital I/O
Pullup
Serial data input 2 for I2S interface or programmable for GPIO #4
SDOUT1
54
Digital output
Serial data output 1 for I2S interface
SDOUT2
53
Digital output
Serial data output 2 for I2S interface
Analog mid supply reference. This pin must be decoupled with a 0.1-
μF
VMID
25
Analog output
low-ESR capacitor and an external 10-
μF filter cap.(4)
Voltage reference for analog supply. A pinout of the internally regulated
1.8-V power. A 0.1-
μF low ESR capacitor and a 4.7-μF filter capacitor
VR_ANA
39
Power
must be connected between this terminal and AVSS_PLL. This terminal
must not be used to power external devices.(4)
Voltage reference for digital supply. A pinout of the internally regulated
1.8-V power. A 0.1-
μF low ESR capacitor and a 4.7-μF filter capacitor
VR_DIG
55
Power
must be connected between this terminal and DVSS. This terminal
must not be used to power external devices.(4)
Voltage reference for DPLL supply. A pinout of internally regulated
1.8-V power supply. A 0.1-
μF low-ESR capacitor and a 4.7-μF filter
VR_PLL
10
Power
capacitor must be connected between this terminal and DVSS. This
terminal must not be used to power external devices.(4)
Bandgap output. A 0.1-
μF low ESR capacitor should be connected
VREF
26
Analog output
between this terminal and AVSS_PLL. This terminal must not be used
to power external devices.(4)
Voltage regulator enable. When enabled LOW, this input causes the
VREG_EN
49
Digital input
power-supply regulators to be enabled.
XTAL_IN
41
Digital input
Crystal input. A 24.576-MHz (512Fs) crystal should be used.
XTAL_OUT
42
Digital output
Crystal output
(4)
If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provide an extended high-frequency supply decoupling.
Copyright 2009–2011, Texas Instruments Incorporated
Physical Characteristics
9
Product Folder Link(s): TAS3202
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