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參數(shù)資料
| 型號： | TAS3204PAGR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 26/76頁 |
| 文件大?。?/td> | 1224K |
| 代理商： | TAS3204PAGR |
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SLES197C – APRIL 2007 – REVISED MARCH 2011
www.ti.com
The checksum is contained in the last two data transfer bytes. These are bytes 7 and 8. On single word
transfers (DAP data, DAP instruction), the checksum is always contained in a 8 byte frame that follows the
last data word, last two bytes. For multiword data register transfers data (MCU Program RAM, MCU
External Data RAM, and DAP Coefficient RAM), the checksum is included in the same byte transfer as
data. To meet the requirement above, the number of words that are transferred contain modulo 8 + 6 in
the case of MCU program and data memory, and modulo 2 + 1 in the case of coefficient memory. When
the slave I2C download is used to replace or update sections of MCU program, MCU data, or DAP
coefficient memory, it is necessary to take these transfer size restrictions into consideration when
determining program, data, and coefficient placements.
The multi word transfers always store first word on the bus at a lower RAM address and increment such
that the last word in the transfer is stored with the highest target RAM address. Consecutive I2C frame
transfers increment target address such that the data in the last transfer is last in target memory address
space.
When the first I2C slave download register is written by the system controller, the TAS3204 updates the
status register by setting a error bit to indicate an error for the memory type that is being loaded. This
error bit is reset when the operation complete and a valid checksum has been received. For example
when the MCU program memory is being loaded, the TAS3204 sets a MCU program memory error
indication in the status register at the start of the sequence. When the last byte of the MCU program
memory and checksum is received, the TAS3204 clears the MCU program memory error indication. This
enables the TAS3204 to preserve any error status indications that occur as a result of incomplete
transfers of data/ checksum error during a series of data and program memory load operations.
The checksum is always contained in the last two bytes of the data block. The I2C slave download is
terminated when a termination header with a zero-length byte-count file is received.
The status register always reflects status of EEPROM boot attempts, unless the user writes to the slave
control register. A write to the slave boot control register causes the EEPROM status register to reflect
slave boot attempt status.
NOTE
Once the MCU program memory has been loaded, further updates to this memory are
prohibited until the device is reset. The TAS3204 I
2C block does respond to the broadcast
address (0x00).
Figure x.x shows the block format of the I2C slave Interface. or other external memory load file. Each line
of the file is a byte (in ASCII format). The checksum is the summation of all the bytes (with beginning and
ending checksum fields = 00). The final checksum inserted into the checksum field is the lowest significant
four bytes of the checksum
Table 8-2. Slave Addresses
Base Address
CS0
R/W
Slave Address
0110 10
0
0x68
0110 10
0
1
0x69
0110 10
1
0
0x6A
0110 10
1
0x6B
32
Copyright 2007–2011, Texas Instruments Incorporated
I2C Control Interface
Product Folder Link(s): TAS3204
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