SLES197C – APRIL 2007 – REVISED MARCH 2011
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Random I2C Transactions
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. For
random I2C read commands, the TAS3204 responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a given subaddress
does not use all 32 bits, the unused bits are read as logic 0. I2C write commands, however, are treated in
accordance with the data assignment for that address space. If a write command is received for a mixer
subaddress, for example, the TAS3204 expects to see five 32-bit words. If fewer than five data words
have been received when a stop command (or another start command) is received, the data received is
discarded.
Sequential I2C Transactions
The TAS3204 also supports sequential I2C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write
transaction has taken place, and the data for all 16 subaddresses is successfully received by the
TAS3204. For I2C sequential write transactions, the subaddress then serves as the start address and the
amount of data subsequently transmitted, before a stop or start is transmitted, determines how many
subaddresses are written to. As was true for random addressing, sequential addressing requires that a
complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data
for the last subaddress is discarded. However, all other data written is accepted; just the incomplete data
is discarded.
Sequential read transactions do not have restrictions on outputting only complete subaddress data sets.
If the master does not issue enough data-received acknowledges to receive all the data for a given
subaddress, the master device simply does not receive all the data.
If the master device issues more data-received acknowledges than required to receive the data for a given
subaddress, the master device simply receives complete or partial sets of data, depending on how many
data-received acknowledges are issued from the subaddress(es) that follow. I2C read transactions, both
sequential and random, can impose wait states.
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I2C Control Interface