參數(shù)資料
型號(hào)： TAS3204PAGR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 67/76頁(yè)
文件大?。?/td> 1224K
代理商： TAS3204PAGR
www.ti.com
SLES197C – APRIL 2007 – REVISED MARCH 2011
TERMINAL
INPUT/
PULLUP/
DESCRIPTION
OUTPUT(1)
PULLDOWN(2)
NAME
NO.
I2C2_SDA
63
Digital I/O
Master I2C serial clock input.
LRCLK_IN
58
Digital Input
Pulldown
Left/right (frame) clock input for I2S interface
LRCLK_OUT
51
Digital Output
Left/right (frame) clock output for I2S interface
MCLK_IN
43
Digital Input
Pulldown
Master clock input for I2S interface. Frequency = 512 x Fs
MCLK_OUT1
48
Digital Output
Master clock output for I2S interface Frequency = 256 x Fs
MCLK_OUT2
47
Digital Output
Programmable master clock output divider
MCLK_OUT3
46
Digital Output
Programmable master clock output divider
This pin needs to be programmed as mute pin in the application code.
MUTE
5
Digital Input
Pulldown
In has no function in default after reset.
Powerdown active LOW. After successful boot, its function is defined by
PDN
7
Digital Input
the boot code.
RESERVED
50
N/A
Pulldown
Pin must be connected to ground
RESET
62
Digital Input
Pullup
Device reset. This pin is active low.
This pin must be connected to a 22 k
(1% tolerance) external resistor
REXT
27
Analog Output
to ground to set analog currents. Trace capacitance must be kept low.
SCLK_IN
59
Digital Input
Serial (bit) clock input for I2S interface
SCLK_OUT
52
Digital Output
Serial (bit) clock output for I2S interface
SDIN1/GPIO3
61
Digital I/O
Pullup
Serial data input #1 for I2S interface / general purpose input/output #3
SDIN2/GPIO4
60
Digital I/O
Pullup
Serial data input #2 for I2S interface / general purpose input/output #4
SDOUT1
54
Digital Output
Serial data output #1 for I2S interface
SDOUT2
53
Digital Output
Serial data output #2 for I2S interface
Analog mid supply reference. This pin must be decoupled with a 0.1-
μF
VMID
25
Analog Output
low-ESR capacitor and an external 10-
μF filter cap.(4)
Voltage reference for analog supply. A pin-out of the internally
regulated 1.8 V power. A 0.1-
μF low ESR capacitor and a 4.7-μF filter
VR_ANA
39
Power
capacitor must be connected between this terminal and AVSS. This
terminal must not be used to power external devices.(4)
Voltage reference for digital supply. A pin-out of the internally regulated
1.8 V power. A 0.1-
μF low ESR capacitor and a 4.7-μF filter capacitor
VR_DIG
55
Power
must be connected between this terminal and DVSS. This terminal
must not be used to power external devices.(4)
Voltage reference for DPLL supply. A pin-out of internally regulated
1.8-V power supply. A 0.1-
μF low-ESR capacitor and a 4.7-μF filter
VR_PLL
10
Power
capacitor must be connected between this terminal and DVSS. This
terminal must not be used to power external devices.(4)
Band gap output. A 0.1-
μF low ESR capacitor should be connected
VREF
26
Analog Output
between this terminal and AVSS. This terminal must not be used to
power external devices.(4)
VREG_EN
49
Digital Input
Voltage regulator enable active low.
XTAL_IN
41
Digital Input
Crystal input. Frequency = 512 x Fs
XTAL_OUT
42
Digital Output
Crystal output. Frequency = 512 x Fs
(4)
If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provide an extended high frequency supply decoupling.
Copyright 2007–2011, Texas Instruments Incorporated
Physical Characteristics
7
Product Folder Link(s): TAS3204
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