參數(shù)資料
型號: TAS5508BPAGG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 31/103頁
文件大?。?/td> 1198K
代理商: TAS5508BPAGG4
7
Biquads
in
Series
Bass
and
Treble
DRC
Bass and Treble
Bypass
Bass
and
Treble
Inline
Pre-
Volume
Post-
Volume
DRC
Bypass
DRC
Inline
B0016-02
From Input Mixer
To Output Mixer
Loudness
Channel Volume
Master
Volume
Max
Volume
TAS5508B
8-Channel Digital Audio PWM Processor
www.ti.com
SLES162C – DECEMBER 2005 – REVISED JULY 2009
All of the TAS5508B default values for DRC can be used except for the DRC1 decay and DRC2 decay.
Table 2-8 shows the recommended time constants and their hex values. If the user wants to implement
other DRC functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE)
tool available from Texas Instruments. The ALE tool allows the user to select the DRC transfer function
graphically. It then outputs the TAS5508B hex coefficients for download to the TAS5508B.
Table 2-8. DRC Recommended Changes From TAS5508B Defaults
I2C
RECOMMENDED TIME
RECOMMENDED
REGISTER FIELDS
DEFAULT HEX
SUBADDRESS
CONSTANT (ms)
HEX VALUE
0x98
DRC1 energy
5
0000 883F
DRC1 (1 – energy)
007F 77C0
0x9C
DRC1 attack
5
0000 883F
DRC1 (1 – attack)
007F 77C0
DRC1 decay
2
0001 538F
0000 00AE
DRC1 (1 – decay)
007E AC70
007F FF51
0x9D
DRC2 energy
5
0000 883F
DRC2 (1 – energy)
007F 77C0
0xA1
DRC2 attack
5
0000 883F
DRC2 (1 – attack)
007F 77C0
DRC2 decay
2
0001 538F
0000 0056
DRC2 (1 – decay)
007E AC70
003F FFA8
Recommended DRC setup flow if the defaults are used:
After power up, load the recommended hex value for DRC1 and DRC2 decay and (1 – decay). See
Enable either the pre-volume or post-volume DRC using I2C registers 0x96 and 0x97. Note that to
avoid a potential timing problem, there should be a 10-ms delay between a write to 0x96 and a write to
0x97.
Recommended DRC setup flow if the DRC design uses values different from the defaults:
After power up, load all DRC coefficients per the DRC design.
Enable either the pre-volume or post-volume DRC. Note that to avoid a potential timing problem, there
should be a 10-ms delay between a write to 0x96 and a write to 0x97.
Figure 2-16 shows the positioning of the DRC block in the TAS5508B processing flow. As seen, the DRC
input can come either before or after soft volume control and loudness processing.
Figure 2-16. DRC Positioning in TAS5508B Processing Flow
Description
33
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