參數(shù)資料
型號(hào): TAS5508BPAGG4
廠(chǎng)商: TEXAS INSTRUMENTS INC
元件分類(lèi): 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù): 49/103頁(yè)
文件大小: 1198K
代理商: TAS5508BPAGG4
TAS5508B
8-Channel Digital Audio PWM Processor
www.ti.com
SLES162C – DECEMBER 2005 – REVISED JULY 2009
List of Figures
1-1
TAS5508B Functional Structure
................................................................................................. 11
1-2
Typical TAS5508B Application (DVD Receiver)
.............................................................................. 13
1-3
Pass-Through Output Mixer TAS5508B Channel Configuration
............................................................ 13
2-1
TAS5508B DAP Architecture With I
2C Registers (f
S ≤ 96 kHz) .............................................................
2-2
TAS5508B Architecture With I
2C Registers (f
S = 176.4 kHz or fS = 192 kHz) ............................................
2-3
TAS5508B Detailed Channel Processing
...................................................................................... 23
2-4
5.23 Format
........................................................................................................................ 24
2-5
Conversion Weighting Factors—5.23 Format to Floating Point
............................................................. 24
2-6
Alignment of 5.23 Coefficient in 32-Bit I
2C Word
............................................................................. 24
2-7
25.23 Format
...................................................................................................................... 25
2-8
Conversion Weighting Factors—25.23 Format to Floating Point
........................................................... 25
2-9
Alignment of 25.23 Coefficient in Two 32-Bit I
2C Words
..................................................................... 26
2-10
TAS5508B Digital Audio Processing
........................................................................................... 27
2-11
Input Crossbar Mixer
............................................................................................................. 27
2-12
Biquad Filter Structure
............................................................................................................ 28
2-13
Automute Threshold
.............................................................................................................. 30
2-14
Loudness Compensation Functional Block Diagram
......................................................................... 31
2-15
Loudness Example Plots
......................................................................................................... 32
2-16
DRC Positioning in TAS5508B Processing Flow
............................................................................. 33
2-17
Dynamic Range Compression (DRC) Transfer Function Structure
........................................................ 34
2-18
Output Mixers
...................................................................................................................... 38
2-19
De-Emphasis Filter Characteristics
............................................................................................. 39
2-20
Power-Supply and Digital Gains (Linear Space)
.............................................................................. 40
2-21
Power-Supply and Digital Gains (Log Space)
................................................................................. 40
2-22
Block Diagrams of Typical Systems Requiring TAS5508B Automatic AM Interference-Avoidance Circuit
........... 41
4-1
Slave Mode Serial Data Interface Timing
...................................................................................... 54
4-2
Start and Stop Conditions Timing Waveforms
................................................................................ 55
4-3
I
2C Pullup Circuit (With No Series Resistor)
................................................................................... 56
4-4
I
2C Pullup Circuit (With Series Resistor)
....................................................................................... 56
4-5
Reset Timing
....................................................................................................................... 57
4-6
Power-Down Timing
.............................................................................................................. 57
4-7
Error-Recovery Timing
........................................................................................................... 58
4-8
Mute Timing
........................................................................................................................ 58
4-9
HP_SEL Timing
................................................................................................................... 59
4-10
I
2S 64-f
S Format ...................................................................................................................
4-11
Left-Justified 64-fS Format ....................................................................................................... 61
4-12
Right-Justified 64-fS Format ..................................................................................................... 62
5-1
Typical I
2C Sequence
............................................................................................................. 63
5-2
Single-Byte Write Transfer
....................................................................................................... 64
List of Figures
5
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