TAS5508
8-Channel Digital Audio PWM Processor
www.ti.com
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
List of Figures
1-1
TAS5508 Functional Structure
..................................................................................................
111-2
Typical TAS5508 Application (DVD Receiver)
................................................................................
121-3
Recommended TAS5508 and TAS5121 Channel Configuraton
............................................................
132-1
TAS5508 DAP Architecture With I
2C Registers (Fs
≤ 96 kHz).............................................................. 22 2-2
TAS5508 Architecture With I
2C Registers (Fs = 176.4 kHz or Fs = 192 kHz)
............................................
232-3
TAS5508 Detailed Channel Processing
........................................................................................
242-4
5.23 Format
........................................................................................................................
252-5
Conversion Weighting Factors—5.23 Format to Floating Point
.............................................................
252-6
Alignment of 5.23 Coefficient in 32-Bit I
2C Word
.............................................................................
252-7
25.23 Format
......................................................................................................................
262-8
Alignment of 5.23 Coefficient in 32-Bit I
2C Word
.............................................................................
262-9
Alignment of 25.23 Coefficient in Two 32-Bit I
2C Words
.....................................................................
272-10
TAS5508 Digital Audio Processing
.............................................................................................
282-11
Input Crossbar Mixer
.............................................................................................................
282-12
Biquad Filter Structure
............................................................................................................
292-13
Automute Threshold
..............................................................................................................
312-14
Loudness Compensation Functional Block Diagram
.........................................................................
322-15
Loudness Example Plots
.........................................................................................................
332-16
DRC Positioning in TAS5508 Processing Flow
...............................................................................
342-17
Dynamic Range Compression (DRC) Transfer Function Structure
........................................................
352-18
Output Mixers
......................................................................................................................
392-19
De-Emphasis Filter Characteristics
.............................................................................................
402-20
Power-Supply and Digital Gains (Log Space)
.................................................................................
412-21
Power-Supply and Digital Gains (Linear Space)
..............................................................................
412-22
Block Diagrams of Typical Systems Requiring TAS5508 Automatic AM Interference-Avoidance Circuit
4-1
Slave Mode Serial Data Interface Timing
......................................................................................
574-2
SCL and SDA Timing
.............................................................................................................
584-3
Start and Stop Conditions Timing
...............................................................................................
584-4
Reset Timing
.......................................................................................................................
594-5
Power-Down Timing
..............................................................................................................
594-6
Error Recovery Timing
...........................................................................................................
604-7
Mute Timing
........................................................................................................................
604-8
HP_SEL Timing
...................................................................................................................
614-9
I
2S 64-Fs Format
..................................................................................................................
624-10
Left-Justified 64-Fs Format
......................................................................................................
634-11
Right-Justified 64-Fs Format
....................................................................................................
645-1
Typical I
2C Sequence
.............................................................................................................
655-2
Single-Byte Write Transfer
.......................................................................................................
665-3
Multiple-Byte Write Transfer
.....................................................................................................
66List of Figures
5