參數(shù)資料
型號(hào): TAS5508PAGR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù): 51/105頁(yè)
文件大小: 1286K
代理商: TAS5508PAGR
TAS5508
8-Channel Digital Audio PWM Processor
www.ti.com
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
List of Figures
1-1
TAS5508 Functional Structure
.................................................................................................. 11
1-2
Typical TAS5508 Application (DVD Receiver)
................................................................................ 12
1-3
Recommended TAS5508 and TAS5121 Channel Configuraton
............................................................ 13
2-1
TAS5508 DAP Architecture With I
2C Registers (Fs
≤ 96 kHz).............................................................. 22
2-2
TAS5508 Architecture With I
2C Registers (Fs = 176.4 kHz or Fs = 192 kHz)
............................................ 23
2-3
TAS5508 Detailed Channel Processing
........................................................................................ 24
2-4
5.23 Format
........................................................................................................................ 25
2-5
Conversion Weighting Factors—5.23 Format to Floating Point
............................................................. 25
2-6
Alignment of 5.23 Coefficient in 32-Bit I
2C Word
............................................................................. 25
2-7
25.23 Format
...................................................................................................................... 26
2-8
Alignment of 5.23 Coefficient in 32-Bit I
2C Word
............................................................................. 26
2-9
Alignment of 25.23 Coefficient in Two 32-Bit I
2C Words
..................................................................... 27
2-10
TAS5508 Digital Audio Processing
............................................................................................. 28
2-11
Input Crossbar Mixer
............................................................................................................. 28
2-12
Biquad Filter Structure
............................................................................................................ 29
2-13
Automute Threshold
.............................................................................................................. 31
2-14
Loudness Compensation Functional Block Diagram
......................................................................... 32
2-15
Loudness Example Plots
......................................................................................................... 33
2-16
DRC Positioning in TAS5508 Processing Flow
............................................................................... 34
2-17
Dynamic Range Compression (DRC) Transfer Function Structure
........................................................ 35
2-18
Output Mixers
...................................................................................................................... 39
2-19
De-Emphasis Filter Characteristics
............................................................................................. 40
2-20
Power-Supply and Digital Gains (Log Space)
................................................................................. 41
2-21
Power-Supply and Digital Gains (Linear Space)
.............................................................................. 41
2-22
Block Diagrams of Typical Systems Requiring TAS5508 Automatic AM Interference-Avoidance Circuit
............. 42
4-1
Slave Mode Serial Data Interface Timing
...................................................................................... 57
4-2
SCL and SDA Timing
............................................................................................................. 58
4-3
Start and Stop Conditions Timing
............................................................................................... 58
4-4
Reset Timing
....................................................................................................................... 59
4-5
Power-Down Timing
.............................................................................................................. 59
4-6
Error Recovery Timing
........................................................................................................... 60
4-7
Mute Timing
........................................................................................................................ 60
4-8
HP_SEL Timing
................................................................................................................... 61
4-9
I
2S 64-Fs Format
.................................................................................................................. 62
4-10
Left-Justified 64-Fs Format
...................................................................................................... 63
4-11
Right-Justified 64-Fs Format
.................................................................................................... 64
5-1
Typical I
2C Sequence
............................................................................................................. 65
5-2
Single-Byte Write Transfer
....................................................................................................... 66
5-3
Multiple-Byte Write Transfer
..................................................................................................... 66
List of Figures
5
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