TAS5508
8-Channel Digital Audio PWM Processor
www.ti.com
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
Table 7-16. Channel 1–8 Input Mixer Register Format
I2C
TOTAL
REGISTER
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUBADDRESS
BYTES
FIELDS
SDIN1-left (Ch1) A to input mixer 1 coefficient (default = 1)
0x00, 0x80, 0x00, 0x00
A_to_ipmix[1]
u[31:28], A_1[27:24], A_1[23:16], A_1[15:8], A_1[7:0]
SDIN1-right (Ch2) B to input mixer 1 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
B_to_ipmix[1]
u[31:28], B_1[27:24], B_1[23:16], B_1[15:8], B_1[7:0]
SDIN2-left (Ch3) C to input mixer 1 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
C_to_ipmix[1]
u[31:28], C_1[27:24], C_1[23:16], C_1[15:8], C_1[7:0]
SDIN2-right (Ch4) D to input mixer 1 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
D_to_ipmix[1]
u[31:28], D_1[27:24], D_1[23:16], D_1[15:8], D_1[7:0]
0x41
32
SDIN3-left (Ch5) E to input mixer 1 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
E_to_ipmix[1]
u[31:28], E_1[27:24], E_1[23:16], E_1[15:8], E_1[7:0]
SDIN3-right (Ch6) F to input mixer 1 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[1]
u[31:28], F_1[27:24], F_1[23:16], F_1[15:8], F_1[7:0]
SDIN4-left (Ch7) G to input mixer 1 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[1]
u[31:28], G_1[27:24], G_1[23:16], G_1[15:8], G_1[7:0]
SDIN4-right (Ch8) H to input mixer 1 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[1]
u[31:28], H_1[27:24], H_1[23:16], H_1[15:8], H_1[7:0]
SDIN1-left (Ch1) A to input mixer 2 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
A_to_ipmix[2]
u[31:28], A_2[27:24], A_2[23:16], A_2[15:8], A_2[7:0]
SDIN1-right (Ch2) B to input mixer 2 coefficient (default = 1)
0x00, 0x80, 0x00, 0x00
B_to_ipmix[2]
u[31:28], B_2[27:24], B_2[23:16], B_2[15:8], B_2[7:0]
SDIN2-left (Ch3) C to input mixer 2 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
C_to_ipmix[2]
u[31:28], C_2[27:24], C_2[23:16], C_2[15:8], C_2[7:0]
SDIN2-right (Ch4) D to input mixer 2 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
D_to_ipmix[2]
u[31:28], D_2[27:24], D_2[23:16], D_2[15:8], D_2[7:0]
0x42
32
SDIN3-left (Ch5) E to input mixer 2 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
E_to_ipmix[2]
u[31:28], E_2[27:24], E_2[23:16], E_2[15:8], E_2[7:0]
SDIN3-right (Ch6) F to input mixer 2 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[2]
u[31:28], F_2[27:24], F_2[23:16], F_2[15:8], F_2[7:0]
SDIN4-left (Ch7) G to input mixer 2 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[2]
u[31:28], G_2[27:24], G_2[23:16], G_2[15:8], G_2[7:0]
SDIN4-right (Ch8) H to input mixer 2 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[2]
u[31:28], H_2[27:24], H_2[23:16], H_2[15:8], H_2[7:0]
SDIN1-left (Ch1) A to input mixer 3 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
A_to_ipmix[3]
u[31:28], A_3[27:24], A_3[23:16], A_3[15:8], A_3[7:0]
SDIN1-right (Ch2) B to input mixer 3 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
B_to_ipmix[3]
u[31:28], B_3[27:24], B_3[23:16], B_3[15:8], B_3[7:0]
SDIN2-left (Ch3) C to input mixer 3 coefficient (default = 1)
0x00, 0x80, 0x00, 0x00
C_to_ipmix[3]
u[31:28], C_3[27:24], C_3[23:16], C_3[15:8], C_3[7:0]
SDIN2-right (Ch4) D to input mixer 3 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
D_to_ipmix[3]
u[31:28], D_3[27:24], D_3[23:16], D_3[15:8], D_3[7:0]
0x43
32
SDIN3-left (Ch5) E to input mixer 3 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
E_to_ipmix[3]
u[31:28], E_3[27:24], E_3[23:16], E_3[15:8], E_3[7:0]
SDIN3-right (Ch6) F to input mixer 3 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[3]
u[31:28], F_3[27:24], F_3[23:16], F_3[15:8], F_3[7:0]
SDIN4-left (Ch7) G to input mixer 3 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[3]
u[31:28], G_3[27:24], G_3[23:16], G_3[15:8], G_3[7:0]
SDIN4-right (Ch8) H to input mixer 3 coefficient (default = 0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[3]
u[31:28], H_3[27:24], H_3[23:16], H_3[15:8], H_3[7:0]
Serial-Control Interface Register Definitions
81