參數(shù)資料
型號: TAS5711PHP
廠商: Texas Instruments
文件頁數(shù): 47/66頁
文件大?。?/td> 0K
描述: IC AMP AUD DGTL 20W 2CH 48HTQFP
標準包裝: 250
類型: D 類
輸出類型: 2 通道(立體聲,2.1)或 4 通道(四路)
在某負載時最大輸出功率 x 通道數(shù)量: 21W x 2 @ 8 歐姆
電源電壓: 8 V ~ 26 V
特點: 消除爆音,數(shù)字輸入,I²C,I²S,靜音,短路和熱保護,關機,音量控制
安裝類型: 表面貼裝
供應商設備封裝: 48-HTQFP(7x7)
封裝/外殼: 48-TQFP 裸露焊盤
包裝: 托盤
其它名稱: 296-32732
TAS5711PHP-ND
www.ti.com
SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010
MODULATION LIMIT REGISTER (0x10)
The modulation limit is the maximum duty cycle of the PWM output waveform.
Table 14. Modulation Limit Register (0x10)
D7
D6
D5
D4
D3
D2
D1
D0
MODULATION LIMIT
0
99.2%
0
1
98.4%
0
1
0
97.7% (1)
0
1
96.9%
1
0
96.1%
1
0
1
95.3%
1
0
94.5%
1
93.8%
0
RESERVED
(1)
Default values are in bold.
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
Internal PWM Channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.
Table 15. Channel Interchannel Delay Register Format
BITS DEFINITION
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
Minimum absolute delay, 0 DCLK cycles
0
1
Maximum positive delay, 31 × 4 DCLK cycles
1
0
Maximum negative delay, –32 × 4 DCLK cycles
0
RESERVED
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Delay = (value) × 4 DCLKs
0x11
1
0
1
0
1
Default value for channel 1 (1)
0x12
0
1
0
1
0
1
Default value for channel 2 (1)
0x13
1
0
1
0
1
Default value for channel 1 (1)
0x14
0
1
0
1
0
1
Default value for channel 2 (1)
(1)
Default values are in bold.
ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk etc.). Therefore,
appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD
mode, then update these registers before coming out of all-channel shutdown.
REGISTER
AD MODE
BD MODE
0x11
AC
B8
0x12
54
60
0x13
AC
A0
0x14
54
48
Copyright 2009–2010, Texas Instruments Incorporated
51
Product Folder Link(s): TAS5711
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