參數(shù)資料
型號: TC850IJL
元件分類: ADC
英文描述: 1-CH 15-BIT MULTI-SLOPE ADC, PARALLEL ACCESS, CDIP40
封裝: CERDIP-40
文件頁數(shù): 11/26頁
文件大小: 417K
代理商: TC850IJL
2006 Microchip Technology Inc.
DS21479C-page 19
TC850
FIGURE 8-6:
Conversion Timing, Continuous Mode
FIGURE 8-7:
Bus Output Timing, Continuous Mode
DB0-DB7
Busy
Internal
Clock
Data Meaningless
Data Valid
Data Meaningless
1/2 Clock Cycle
836 Clock Cycles
1280 Internal Clock Cycles
443-1/2 Clock
Cycles
. . . . . . .
. . . . .
RD
BUSY
CONT/DEMAND
DB0-DB7
NOTES: CS = HIGH; CE = LOW
Data Bits 0-7
Data Bits 8-14
Overrange
High-Impedance
State
HI-Z
TRE
TWRE
TWRD
Data Bits 8-14
Polarity
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