參數(shù)資料
型號(hào)： TC850IJL
元件分類(lèi)： ADC
英文描述： 1-CH 15-BIT MULTI-SLOPE ADC, PARALLEL ACCESS, CDIP40
封裝： CERDIP-40
文件頁(yè)數(shù)： 5/26頁(yè)
文件大?。?/td> 417K
代理商： TC850IJL
2006 Microchip Technology Inc.
DS21479C-page 13
TC850
TABLE 6-1:
BUS INTERFACE TRUTH TABLE
CE CS
Pins 1 and 2
RD
Pin 4
CONT/DEMAND
Pin 5
L/H
Pin 7
OVR/POL
Pin 6
DB7
Pin 8
DB6–DB0
Pin 9-Pin 15 (Note 1)
00
0
“1” = Input Positive
Data Bits 14 - 8
00
0
1
“1” = Input Overrange
Data Bits 14 - 8
00
0
1
X
Data Bit 7
Data Bits 6 - 0
00
1
X
01
X
High-Impedance State
1X
X
High-Impedance State
Note
1:
Pin numbers refer to 40-pin PDIP.
2: Extended overrange operation: Although rated at 15 bits (±32,767 counts) of resolution, the TC850 provides an addi-
tional 191 counts above full scale. For example, with a full-scale input of 3.2768V, the maximum analog input voltage
which will be properly converted is 3.2958V. The extended resolution is signified by the overrange bit being high and the
low-order byte contents being between 0 and 190. For example, with a full-scale voltage of 3.2768V:
VIN
Overrange Bit
Low Byte
Data Bits 14–8
3.2767V
Low
25510
12710
3.2768V
High
00010
010
3.2769V
High
00110
010
3.2867V
High
09910
010
3: Continuous mode data transfer:
a. In Continuous mode, data MUST be read in three sequential bytes after the BUSY output goes low:
(1) The first byte read will be the high-order byte, with DB7 = polarity.
(2) The second byte read will contain the low-order byte.
(3) The third byte read will again be the high-order byte, but with DB7 = overrange.
b. All three data bytes must be read within 443-1/2 clock cycles after the falling edge of BUSY.
c.
The c input must go high after each byte is read, so that the internal byte counter will be incremented.
However, the CS and CEinputs can remain enabled through the entire data transfer sequence.
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