參數(shù)資料
型號： TDA6500TT/C4,118
廠商： NXP SEMICONDUCTORS
元件分類： 調(diào)諧器
英文描述： 3-BAND, VIDEO TUNER, PDSO32
封裝： 6.10 MM, 0.65 MM PITCH, PLASTIC, MO-153, SOT487-1, TSSOP-32
文件頁數(shù)： 34/37頁
文件大?。?/td> 223K
代理商： TDA6500TT/C4,118
9397 750 15057
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 14 June 2005
6 of 37
Philips Semiconductors
TDA6500; TDA6501
5 V mixer/oscillator and synthesizer for PAL and NTSC standards
The AGC detector provides information about the IF amplier level. Five AGC take-over
points are available by software. Two programmable AGC time constants are available for
search tuning and normal tuner operation. The synthesizer consists of a 15-bit
programmable divider, a crystal oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge pump, which drives the tuning amplier
including 33 V output.
Depending on the reference divider ratio (64, 80 or 128) the phase comparator operates
at 62.50 kHz, 50.00 kHz or 31.25 kHz with a 4 MHz crystal.
The device can be controlled according to the I2C-bus format. The lock detector bit FL is
set to logic 1 when the loop is locked. The AGC bit is set to logic 1 when the internal AGC
is active (level below 3 V). These two ags are read on the SDA line (status byte) during a
read operation (see Table 11).
The ADC input is available on pin P6/ADC for digital AFC control. The ADC code is read
during a read operation (see Table 11). In test mode, pin P6/ADC is used as a test output
for 1
2fref and
1
2fdiv (see Table 8).
A minimum of seven bytes, including address byte, is required to address the device,
select the VCO frequency, program the ports, set the charge pump current, set the
reference divider ratio, select the AGC take-over point and select the AGC time constant.
The device has four independent I2C-bus addresses which can be selected by applying a
specic voltage on input AS (see Table 7).
7.2 Device control
The device is controlled via the I2C-bus. For programming, a module address of 7 bits and
the R/W bit for selecting the read or the write mode is required.
7.2.1 Write mode
Data bytes can be sent to the device after the address transmission (rst byte). Seven
data bytes are needed to fully program the device. The bus transceiver has an
auto-increment facility, which permits the programming of the device within one single
transmission (address + 6 data bytes).
The device can also be partially programmed providing that the rst data byte following
the address is the rst divider byte DB1 or the control byte CB. The data bytes are dened
The rst bit of the rst data byte indicates whether frequency data (rst bit = 0) or control,
port and auxiliary data (rst bit = 1) will follow. Until an I2C-bus STOP command is sent by
the controller, additional data bytes can be entered without the need to re-address the
device. The frequency register is loaded with data from byte DB2 after the 8th SCL clock
Table 4:
Mixer and oscillator band selection
Bit
Mixer band
Oscillator band
P0
P1
low
mid
high
low
mid
high
10x
x
01
x
00
x
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