參數(shù)資料
型號: TDA6650ATT/C3
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO38
封裝: 4.40 MM, 0.50 MM PITCH, PLASTIC, MO-153, SOT510-1, TSSOP-38
文件頁數(shù): 4/54頁
文件大?。?/td> 325K
代理商: TDA6650ATT/C3
TDA6650ATT_6651ATT_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 2 February 2007
12 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
8.2 Read mode; R/W=1
Data can be read from the device by setting the R/W bit to 1 (see Table 13). After the
device address has been recognized, the device generates an acknowledge pulse and the
rst data byte (status byte) is transferred on the SDA line (MSB rst). Data is valid on the
SDA line during a HIGH level of the SCL clock signal.
A second data byte can be read from the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge). End of transmission will occur if no
master acknowledge occurs. The device will then release the data line to allow the
microcontroller to generate a STOP condition.
[1]
MSB is transmitted rst.
1016
254
1107
400
1118
580
Table 12.
Charge pump current …continued
CP2
CP1
CP0
Charge pump current
number
Typical current (absolute
value in
A)
Table 13.
I2C-bus read data format
Name
Byte
Bit
Ack
LSB
Address byte 1
1
0
MA1
MA0
R/W=1 A
Status byte
2
POR
FL
0
1
AGC
A2
A1
A0
-
Table 14.
Description of read data format bits
Bit
Description
A
acknowledge
POR
power-on reset ag
POR = 0, normal operation
POR = 1, power-on reset
FL
in-lock ag
FL = 0, not locked
FL = 1, the PLL is locked
AGC
internal AGC ag
AGC = 0 when internal AGC is active (VAGC < VRML)
AGC = 1 when internal AGC is not active (VAGC > VRMH)
A2, A1, A0
digital outputs of the 5-level ADC; see Table 15
Table 15.
ADC levels
Voltage applied to pin ADC[1]
A2
A1
A0
0.6VCC to VCC
100
0.45VCC to 0.6VCC
011
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