參數(shù)資料
型號(hào): TDA6650ATT/C3
廠(chǎng)商: NXP SEMICONDUCTORS
元件分類(lèi): 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO38
封裝: 4.40 MM, 0.50 MM PITCH, PLASTIC, MO-153, SOT510-1, TSSOP-38
文件頁(yè)數(shù): 5/54頁(yè)
文件大?。?/td> 325K
代理商: TDA6650ATT/C3
TDA6650ATT_6651ATT_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 2 February 2007
13 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
[1]
Accuracy is
±0.03VCC. Bit BS5 must be set to logic 0 to disable the BS5 output port. The BS5 output port
uses the same pin as the ADC and can not be used when the ADC is in use.
8.3 Status at power-on reset
At power on or when the supply voltage drops below approximately 2.85 V (at
Tamb =25 °C), internal registers are set according to Table 16.
At power on, the charge pump current is set to 580
A, the test bits T[2:0] are set to 110
which means that the charge pump is sinking current, the tuning voltage output is
disabled. The XTOUT buffer is on, driving the 4 MHz signal from the crystal oscillator and
all the ports are off. As a consequence, the high band is selected by default.
[1]
X means that this bit is not set or reset at power-on reset.
[2]
The next six bits are written, when bit T/A = 1 in a write sequence.
[3]
The next six bits are written, when bit T/A = 0 in a write sequence.
0.3VCC to 0.45VCC
010
0.15VCC to 0.3VCC
001
0 V to 0.15VCC
000
Table 15.
ADC levels …continued
Voltage applied to pin ADC[1]
A2
A1
A0
Table 16.
Default setting at power-on reset
Name
Byte
MSB
LSB
Address byte
1
0
MA1
MA0
X
Divider byte 1 (DB1)
2
0
N14 = X
N13 = X
N12 = X
N11 = X
N10 = X
N9 = X
N8 = X
Divider byte 2 (DB2)
3
N7 = X
N6 = X
N5 = X
N4 = X
N3 = X
N2 = X
N1 = X
N0 = X
Control byte 1 (CB1)
4
1
T/A = X[2]
T2 =1
T1 =1
T0 =0
R2=X
R1=X
R0=X
1
T/A = X[3]
0
ATC=0
AL2=0
AL1=1
AL0=0
Control byte 2 (CB2)
5
CP2 = 1
CP1 = 1
CP0 = 1
BS5 = 0
BS4 = 0
BS3 = 0
BS2 = 0
BS1 = 0
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