參數(shù)資料
型號： TDA7580
廠商： 意法半導(dǎo)體
英文描述： FM/AM DIGITAL IF SAMPLING PROCESSOR
中文描述： 調(diào)頻/調(diào)幅數(shù)字IF采樣處理器
文件頁數(shù)： 21/31頁
文件大?。?/td> 450K
代理商： TDA7580
21/31
TDA7580
I
2
C TIMING
Figure 11. DSP and RDS I
2
C BUS Timings.
Symbol
Parameter
Test Condition
Standard Mode
I
2
C BUS
Fast Mode
I
2
C BUS
Unit
Min.
Max.
Min.
Max.
F
SCL
SCLl clock frequency
0
100
0
400
kHz
t
BUF
Bus free between a STOP and
Start Condition
4.7
–
1.3
–
μ
s
t
HD:STA
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated
4.0
–
0.6
–
μ
s
t
LOW
LOW period of the SCL clock
4.7
–
1.3
–
μ
s
t
HIGH
HIGH period of the SCL clock
4.0
–
0.6
–
μ
s
t
SU:STA
Set-up time for a repeated start
condition
4.7
–
0.6
–
μ
s
t
HD:DAT
DATA hold time
0
–
0
0.9
μ
s
t
R
Rise time of both SDA and SCL
signals
Cb in pF
–
1000
20+
0.1C
b
300
ns
t
F
Fall time of both SDA and SCL
signals
Cb in pF
–
300
20+
0.1C
b
300
ns
t
SU;STO
Set-up time for STOP condition
4
–
0.6
–
μ
s
t
SU:DAT
Data set-up time
250
--
--
100
ns
C
b
Capacitive load for each bus line
–
400
–
400
pF
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參數(shù)描述
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